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1. 发明授权

US08539311B2 System and method for data recovery in multi-level cell memories 有权
标题翻译：用于多级单元存储器中的数据恢复的系统和方法
公开(公告)号：US08539311B2
公开(公告)日：2013-09-17
申请号：US13117008
申请日：2011-05-26
申请人： Avi Steiner , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
发明人： Avi Steiner , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3404
摘要： A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.
摘要翻译：提供了一种用于多级单元存储器件中的数据恢复的系统和方法。可以在存储器件中的多级单元的一个或多个相应级别中顺序编程一个或多个位。可以检测到在多级单元的后续第二级或更高级别中编程后续位的中断。可以从定义在第二或更高级别的编程中断之前编程的一个或多个位的多级单元恢复数据。

2. 发明申请

US20120005558A1 SYSTEM AND METHOD FOR DATA RECOVERY IN MULTI-LEVEL CELL MEMORIES 有权
标题翻译：用于数据恢复在多层细胞记忆中的系统和方法
公开(公告)号：US20120005558A1
公开(公告)日：2012-01-05
申请号：US13117008
申请日：2011-05-26
申请人： Avi STEINER , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
发明人： Avi STEINER , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3404
摘要： A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.
摘要翻译：提供了一种用于多级单元存储器件中的数据恢复的系统和方法。可以在存储器件中的多级单元的一个或多个相应级别中顺序编程一个或多个位。可以检测到在多级单元的后续第二级或更高级别中编程后续位的中断。可以从定义在第二或更高级别的编程中断之前编程的一个或多个位的多级单元恢复数据。

3. 发明申请

US20100131831A1 LOW POWER CHIEN-SEARCH BASED BCH/RS DECODING SYSTEM FOR FLASH MEMORY, MOBILE COMMUNICATIONS DEVICES AND OTHER APPLICATIONS 有权
标题翻译：用于闪存存储器，移动通信设备和其他应用的基于低功率基于搜索的BCH / RS解码系统
公开(公告)号：US20100131831A1
公开(公告)日：2010-05-27
申请号：US12595971
申请日：2008-09-17
申请人： Hanan Weingarten , Eli Sterin , Ofir Avraham Kanter , Michael Katz
发明人： Hanan Weingarten , Eli Sterin , Ofir Avraham Kanter , Michael Katz
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/1545 , H03M13/6502
摘要： A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied.
摘要翻译：一种采用Chien搜索电路的低功率Chien搜索方法，该搜索电路包括至少两个硬件组件，所述至少两个硬件组件计算包括Chien搜索输出的至少两个对应位，所述方法包括仅激活硬件组件的子集，从而仅计算 Chien搜索输出; 以及激活硬件组件子集以外的硬件组件，仅在满足Chien搜索输出的比特子集的标准的情况下才计算比特子集中的比特之外的Chien搜索输出的附加比特。

4. 发明授权

US08607128B2 Low power chien-search based BCH/RS decoding system for flash memory, mobile communications devices and other applications 有权
标题翻译：用于闪存，移动通信设备和其他应用的基于低功率基于搜索的BCH / RS解码系统
公开(公告)号：US08607128B2
公开(公告)日：2013-12-10
申请号：US12595971
申请日：2008-09-17
申请人： Hanan Weingarten , Eli Sterin , Ofir Avraham Kanter , Michael Katz
发明人： Hanan Weingarten , Eli Sterin , Ofir Avraham Kanter , Michael Katz
IPC分类号： H03M13/00
CPC分类号： H03M13/1545 , H03M13/6502
摘要： A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied.
摘要翻译：一种采用Chien搜索电路的低功率Chien搜索方法，该搜索电路包括至少两个硬件组件，所述至少两个硬件组件计算包括Chien搜索输出的至少两个对应位，所述方法包括仅激活硬件组件的子集，从而仅计算 Chien搜索输出; 以及激活硬件组件子集以外的硬件组件，仅在满足Chien搜索输出的比特子集的标准的情况下才计算比特子集中的比特之外的Chien搜索输出的附加比特。

5. 发明授权

US08694715B2 Methods for adaptively programming flash memory devices and flash memory systems incorporating same 有权
标题翻译：自适应地编程闪存设备和并入其的闪存系统的方法
公开(公告)号：US08694715B2
公开(公告)日：2014-04-08
申请号：US12596680
申请日：2008-09-17
申请人： Hanan Weingarten , Erez Sabbag , Michael Katz
发明人： Hanan Weingarten , Erez Sabbag , Michael Katz
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/349
摘要： A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit.
摘要翻译：一种用于使用编程处理将多个数据序列编程到相应的多个闪速存储器功能单元中的方法，所述编程处理具有控制给定数据序列的编程过程的持续时间的至少一个可选择的编程持续时间控制参数，所述方法包括：至少一个变化的情境特征的指示，并且至少部分地基于每个闪存功能单元确定用于所述至少一个可选择的编程持续时间控制参数的值，用于控制给定数据序列的编程过程的持续时间所述指示所述变化的特征; 并且对于来自所述多个闪存功能单元的每个单独的闪速存储器功能单元，使用具有至少一个可选参数的编程处理将一系列比特编程到所述单独闪存功能单元中，所述至少一个可选参数被设置以所述个别闪存功能单元确定的所述值。

6. 发明授权

US08508995B2 System and method for adjusting read voltage thresholds in memories 有权
标题翻译：用于调整存储器中读取电压阈值的系统和方法
公开(公告)号：US08508995B2
公开(公告)日：2013-08-13
申请号：US13231354
申请日：2011-09-13
申请人： Hanan Weingarten , Erez Sabbag , Michael Katz
发明人： Hanan Weingarten , Erez Sabbag , Michael Katz
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C11/5628 , G11C16/0483
摘要： A system and method for adjusting read threshold voltage values, for example, in a read circuit internal to a memory device. The quality of an associated read result may be estimated for each read threshold voltage value used to read memory cells. Only read results estimated to have sufficient quality may be allowed to pass to storage. The read threshold voltage value may be adjusted for subsequent read operations, for example, if the associated read result is estimated to have insufficient quality. The read threshold voltage value may be iteratively adjusted, for example, until a read result is estimated to have sufficient quality.
摘要翻译：一种用于调整读取阈值电压值的系统和方法，例如在存储器件内部的读取电路中。可以针对用于读取存储器单元的每个读取阈值电压值来估计相关读取结果的质量。估计只能读取具有足够质量的结果可能被允许传递到存储。可以针对随后的读取操作调整读取阈值电压值，例如，如果相关联的读取结果被估计为具有不足的质量。读取阈值电压值可以被迭代地调整，例如，直到读取结果被估计为具有足够的质量。

7. 发明申请

US20100146192A1 METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME 有权
标题翻译：用于适应性编程FLASH存储器件的方法和包含其的闪存存储器系统
公开(公告)号：US20100146192A1
公开(公告)日：2010-06-10
申请号：US12596680
申请日：2008-09-17
申请人： Hanan Weingarten , Erez Sabbag , Michael Katz
发明人： Hanan Weingarten , Erez Sabbag , Michael Katz
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/349
摘要： A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit.
摘要翻译：一种用于使用编程处理将多个数据序列编程到相应的多个闪速存储器功能单元中的方法，所述编程处理具有控制给定数据序列的编程过程的持续时间的至少一个可选择的编程持续时间控制参数，所述方法包括：至少一个变化的情境特征的指示，并且至少部分地基于每个闪存功能单元确定用于所述至少一个可选择的编程持续时间控制参数的值，用于控制给定数据序列的编程过程的持续时间所述指示所述变化的特征; 并且对于来自所述多个闪存功能单元的每个单独的闪速存储器功能单元，使用具有至少一个可选参数的编程处理将一系列比特编程到所述单独闪存功能单元中，所述至少一个可选参数被设置以所述个别闪存功能单元确定的所述值。

8. 发明授权

US08341335B2 Flash memory apparatus with a heating system for temporarily retired memory portions 有权
标题翻译：具有用于临时退休存储器部分的加热系统的闪存装置
公开(公告)号：US08341335B2
公开(公告)日：2012-12-25
申请号：US12596446
申请日：2008-09-17
申请人： Hanan Weingarten , Shmuel Levy , Michael Katz
发明人： Hanan Weingarten , Shmuel Levy , Michael Katz
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F2212/1032 , G11C16/349
摘要： Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time.
摘要翻译：包括多个存储器部分的闪速存储装置以及在第一持续时间内至少在第一持续时间内仅保留来自所述多个存储器部分中的某些部分包括分配数据的操作的操作的控制器，，仅限于某些部分，从而将多个存储部分中的至少一个除了某些部分之外，作为第一持续时间的退休存储器部分。

9. 发明申请

US20100088557A1 SYSTEMS AND METHODS FOR MULTIPLE CODING RATES IN FLASH DEVICES 有权
标题翻译： FLASH设备中多种编码速率的系统和方法
公开(公告)号：US20100088557A1
公开(公告)日：2010-04-08
申请号：US12595959
申请日：2008-09-17
申请人： Hanan Weingarten , Michael Katz
发明人： Hanan Weingarten , Michael Katz
IPC分类号： G06F12/02 , G06F11/00
CPC分类号： G06F11/1068 , G11C29/82 , G11C2029/0411
摘要： A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the flash memory location; and selecting the encoding rate as a function of the effective error rate such that the number of redundancy bytes is sufficient to overcome the anticipated rate of expected reading errors with a predetermined degree of certainty.
摘要翻译：一种用于编码从主机到达的信息以便将编码信息存储在闪速存储器中的信息的系统和方法，所述方法包括编码从主机到达的信息，以在闪速存储器位置存储，包括生成多个冗余字节，编码步骤所述编码速率是所生成的冗余字节数的函数，所述编码包括确定对于所述闪存位置的预期读取错误率的有效误差率; 以及选择编码率作为有效错误率的函数，使得冗余字节数足以以预定的确定度来克服预期读取错误的预期速率。

10. 发明授权

US08838937B1 Methods, systems and computer readable medium for writing and reading data 有权
标题翻译：用于写入和读取数据的方法，系统和计算机可读介质
公开(公告)号：US08838937B1
公开(公告)日：2014-09-16
申请号：US13478706
申请日：2012-05-23
申请人： Michael Katz , Hanan Weingarten
发明人： Michael Katz , Hanan Weingarten
IPC分类号： G06F9/26 , G06F9/34
CPC分类号： G06F12/0246 , G06F2212/1044 , G06F2212/7201 , G06F2212/7203
摘要： A flash memory controller, a computer readable medium and a method for writing to a flash memory device, the method may include receiving multiple logical pages, each logical page having a logical address; determining to write a logical page into a selected physical page of the flash memory device; calculating a hash value for each logical page of the multiple logical pages in response to (a) a logical address of the logical page and (b) a physical page index, to provide multiple hash values of the multiple logical pages.
摘要翻译：闪速存储器控制器，计算机可读介质和用于写入闪存器件的方法，所述方法可以包括接收多个逻辑页，每个逻辑页具有逻辑地址; 确定将逻辑页面写入到所述闪存设备的所选择的物理页面中; 响应于（a）逻辑页面的逻辑地址和（b）物理页面索引来计算多个逻辑页面中每个逻辑页面的每个逻辑页面的哈希值，以提供多个逻辑页面的多个哈希值。

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