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1. 发明申请

US20120293353A1 OPERATIONAL AMPLIFIER 有权
标题翻译：操作放大器
公开(公告)号：US20120293353A1
公开(公告)日：2012-11-22
申请号：US13468126
申请日：2012-05-10
申请人： Atsushi OKUMURA , Ryusuke Sahara , Mitsugi Kusunoki
发明人： Atsushi OKUMURA , Ryusuke Sahara , Mitsugi Kusunoki
IPC分类号： H03M1/66 , H03F1/34
CPC分类号： H03F3/45475 , H03F3/45928 , H03F2200/447 , H03F2203/45522 , H03F2203/45528 , H03F2203/45534 , H03F2203/45591 , H03F2203/45594 , H03F2203/45616
摘要： A temperature dependence adjustable operational amplifier circuit which suppresses a change in a gain caused by a change in an input voltage is provided. In an operational amplifier including a first input terminal and an output terminal, an operational amplifier having an inverting input terminal and a non-inverting input terminal, an input resistance circuit, and a feedback resistance circuit, each of the input and feedback resistor circuits has a resistor and a trimming resistor, which are different in temperature coefficient from each other, connected in series with each other, and a source-drain path of a MOS transistor included in the trimming resistor circuit is disposed between resistance and an inverting input terminal, and a substrate potential thereof is set to a potential of the inverting input terminal of the operational amplifier.
摘要翻译：提供了抑制由输入电压变化引起的增益变化的温度依赖性可调运算放大器电路。在包括第一输入端子和输出端子的运算放大器中，具有反相输入端子和非反相输入端子的运算放大器，输入电阻电路和反馈电阻电路，每个输入和反馈电阻电路具有电阻和微调电阻彼此串联连接的温度系数彼此不同，并且包括在微调电阻电路中的MOS晶体管的源极 - 漏极路径被设置在电阻和反相输入端之间，并且其衬底电位被设置为运算放大器的反相输入端的电位。

2. 发明授权

US08497791B2 Operational amplifier 有权
标题翻译：运算放大器
公开(公告)号：US08497791B2
公开(公告)日：2013-07-30
申请号：US13468126
申请日：2012-05-10
申请人： Atsushi Okumura , Ryusuke Sahara , Mitsugu Kusunoki
发明人： Atsushi Okumura , Ryusuke Sahara , Mitsugu Kusunoki
IPC分类号： H03M1/10
CPC分类号： H03F3/45475 , H03F3/45928 , H03F2200/447 , H03F2203/45522 , H03F2203/45528 , H03F2203/45534 , H03F2203/45591 , H03F2203/45594 , H03F2203/45616
摘要： A temperature dependence adjustable operational amplifier circuit which suppresses a change in a gain caused by a change in an input voltage is provided. In an operational amplifier including a first input terminal and an output terminal, an operational amplifier having an inverting input terminal and a non-inverting input terminal, an input resistance circuit, and a feedback resistance circuit, each of the input and feedback resistor circuits has a resistor and a trimming resistor, which are different in temperature coefficient from each other, connected in series with each other, and a source-drain path of a MOS transistor included in the trimming resistor circuit is disposed between resistance and an inverting input terminal, and a substrate potential thereof is set to a potential of the inverting input terminal of the operational amplifier.
摘要翻译：提供了抑制由输入电压变化引起的增益变化的温度依赖性可调运算放大器电路。在包括第一输入端子和输出端子的运算放大器中，具有反相输入端子和非反相输入端子的运算放大器，输入电阻电路和反馈电阻电路，每个输入和反馈电阻电路具有电阻和微调电阻彼此串联连接的温度系数彼此不同，并且包括在微调电阻电路中的MOS晶体管的源极 - 漏极路径被设置在电阻和反相输入端之间，并且其衬底电位被设置为运算放大器的反相输入端的电位。

3. 发明授权

US07078928B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07078928B2
公开(公告)日：2006-07-18
申请号：US10736673
申请日：2003-12-17
申请人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
发明人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
IPC分类号： H03K19/00 , G01R31/28 , H03H11/26
CPC分类号： G01R31/318577
摘要： The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.
摘要翻译：本发明提供一种配备有至少一个脉冲发生器的半导体集成电路器件，该脉冲发生器产生的脉冲脉冲短于传输信号的全幅度的上升时间。通过第一信号路径和第二信号路径从外部提供的第一信号和第二信号分别传送到脉冲发生器。当在第一信号路径和第二信号路径中的任何一个缓冲器上的上升时间达到全幅度时，脉冲发生器将形成的脉冲的脉冲宽度大于第一信号与第二信号路径之间的相位差使第二信号对应于第一脉冲的脉冲宽度。

4. 发明申请

US20060245266A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060245266A1
公开(公告)日：2006-11-02
申请号：US11409963
申请日：2006-04-25
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： G11C7/10
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。因此，可以提高D / A转换器的性能。

5. 发明授权

US07522083B2 Semiconductor device having D/A conversion portion 有权
标题翻译：具有D / A转换部分的半导体器件
公开(公告)号：US07522083B2
公开(公告)日：2009-04-21
申请号：US11877561
申请日：2007-10-23
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： H03M1/78
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。因此，可以提高D / A转换器的性能。

6. 发明申请

US20120013220A1 PIEZOELECTRIC ACTUATOR DRIVE UNIT 审中-公开
标题翻译：压电致动器驱动单元
公开(公告)号：US20120013220A1
公开(公告)日：2012-01-19
申请号：US13182846
申请日：2011-07-14
申请人： Takahiro KAWATA , Ryusuke Sahara , Satoshi Ueno
发明人： Takahiro KAWATA , Ryusuke Sahara , Satoshi Ueno
IPC分类号： H01L41/09
CPC分类号： H02N2/0075 , B06B1/0269 , B06B1/06 , B06B2201/55 , B06B2201/70 , G06F3/016
摘要： Disclosed is a piezoelectric actuator drive unit that includes a piezoelectric actuator drive amplifier and a piezoelectric actuator drive unit power supply. Combinations of high and low signal levels of a first control signal, which controls the supply voltage and amplifier bias voltage of the piezoelectric actuator drive amplifier, and a second control signal, which controls the driving force of the piezoelectric actuator drive amplifier, are associated with a haptic feedback function, a receiver function for generating an audio output, and a speaker function for generating music or the like. Thus, the piezoelectric actuator drive unit, which vibrates a piezoelectric actuator, is adapted to the haptic feedback function, the receiver function, and the speaker function, and can optimize its power and drive amplifier characteristics.
摘要翻译：公开了一种压电致动器驱动单元，其包括压电致动器驱动放大器和压电致动器驱动单元电源。控制压电致动器驱动放大器的电源电压和放大器偏置电压的第一控制信号的高和低信号电平的组合以及控制压电致动器驱动放大器的驱动力的第二控制信号与触觉反馈功能，用于产生音频输出的接收机功能，以及用于产生音乐等的扬声器功能。因此，振动压电致动器的压电致动器驱动单元适合于触觉反馈功能，接收器功能和扬声器功能，并且可以优化其功率和驱动放大器特性。

7. 发明授权

US07310266B2 Semiconductor device having memory cells implemented with bipolar-transistor-antifuses operating in a first and second mode 有权
标题翻译：具有以第一和第二模式工作的双极晶体管 - 反熔丝实现的存储单元的半导体器件
公开(公告)号：US07310266B2
公开(公告)日：2007-12-18
申请号：US11409963
申请日：2006-04-25
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： G11C11/40 , H03M1/66
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结点是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。

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