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1. 发明申请

US20110276966A1 Managing task dependency within a data processing system 审中-公开
标题翻译：管理数据处理系统中的任务依赖关系
公开(公告)号：US20110276966A1
公开(公告)日：2011-11-10
申请号：US12662857
申请日：2010-05-06
申请人： Aske Simon Christensen , Sean Ellis , Andreas Engh-Halstvedt
发明人： Aske Simon Christensen , Sean Ellis , Andreas Engh-Halstvedt
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F2209/506
摘要： A processing apparatus includes task manager circuitry 14 issuing task specifiers to processing circuitry 16, 18, 20, 22, 24 indicating processing tasks to be performed. The task specifier includes a relaxed dependency identifier to which the processing circuitry is responsive. The processing circuitry responds to the relaxed dependency identifier by starting the processing task concerned and then controlling the processing task concerned in dependency upon the status of the other processing task upon which there is a relaxed dependency. The task specifier may also indicate a strict dependency in which a processing task may not be started until the other processing task has completed as well as a no dependency indication in which the processing task may be started without reference to any other processing task.
摘要翻译：处理装置包括任务管理器电路14，其向处理电路16,18,20,22,24发出指示要执行的处理任务的任务说明符。任务说明符包括处理电路响应的松弛依赖标识符。处理电路通过启动有关的处理任务来响应松弛依赖标识符，然后依赖于存在松弛依赖性的其他处理任务的状态来控制有关的处理任务。任务说明符还可以指示在其他处理任务已经完成之前处理任务可能不开始的严格依赖关系，以及在不参考任何其他处理任务的情况下可以启动处理任务的不依赖性指示。

2. 发明申请

US20120007878A1 Switching between dedicated function hardware and use of a software routine to generate result data 有权
标题翻译：在专用功能硬件之间切换并使用软件程序生成结果数据
公开(公告)号：US20120007878A1
公开(公告)日：2012-01-12
申请号：US13067570
申请日：2011-06-09
申请人： Simon Jones , Andreas Engh-Halstvedt , Aske Simon Christensen
发明人： Simon Jones , Andreas Engh-Halstvedt , Aske Simon Christensen
IPC分类号： G06T1/00 , G09G5/02
CPC分类号： G06F9/30189 , G06F9/30058 , G06F9/30145 , G06F9/3877
摘要： An apparatus for processing data 2 is provided including processing circuitry 24 controlled by an instruction decoder 20 in response to a stream of program instructions. There is also provided dedicated function hardware 12 configured to receive output data from the processing circuitry and to perform a dedicated processing operation. The instruction decoder 20 is responsive to an end instruction 54 and a software processing flag (blend_shade_enabled) to control the processing circuitry to end a current software routine, to generate output data and in dependence upon the software processing flag either trigger processing of the output data by the dedicated function hardware or trigger the processing circuitry to perform a further software routine upon the output data to generate software generated result data instead of hardware generated result data as generated by the dedicated hardware circuitry.
摘要翻译：提供了一种用于处理数据2的装置，其包括响应于程序指令流由指令解码器20控制的处理电路24。还提供了专用功能硬件12，其被配置为从处理电路接收输出数据并执行专用处理操作。指令解码器20响应于结束指令54和软件处理标志（blend_shade_enabled）来控制处理电路以结束当前软件程序，以产生输出数据，并根据软件处理标志触发输出数据的处理通过专用功能硬件或触发处理电路，以在输出数据上执行另外的软件程序以产生软件产生的结果数据，而不是由专用硬件电路产生的硬件产生的结果数据。

3. 发明授权

US08922568B2 Switching between dedicated function hardware and use of a software routine to generate result data 有权
标题翻译：在专用功能硬件之间切换并使用软件程序生成结果数据
公开(公告)号：US08922568B2
公开(公告)日：2014-12-30
申请号：US13067570
申请日：2011-06-09
申请人： Simon Jones , Andreas Engh-Halstvedt , Aske Simon Christensen
发明人： Simon Jones , Andreas Engh-Halstvedt , Aske Simon Christensen
IPC分类号： G06T1/00 , G06F13/14 , G06F7/38 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30189 , G06F9/30058 , G06F9/30145 , G06F9/3877
摘要： An apparatus for processing data 2 is provided including processing circuitry 24 controlled by an instruction decoder 20 in response to a stream of program instructions. There is also provided dedicated function hardware 12 configured to receive output data from the processing circuitry and to perform a dedicated processing operation. The instruction decoder 20 is responsive to an end instruction 54 and a software processing flag (blend_shade_enabled) to control the processing circuitry to end a current software routine, to generate output data and in dependence upon the software processing flag either trigger processing of the output data by the dedicated function hardware or trigger the processing circuitry to perform a further software routine upon the output data to generate software generated result data instead of hardware generated result data as generated by the dedicated hardware circuitry.
摘要翻译：提供了一种用于处理数据2的装置，其包括响应于程序指令流由指令解码器20控制的处理电路24。还提供了专用功能硬件12，其被配置为从处理电路接收输出数据并执行专用处理操作。指令解码器20响应于结束指令54和软件处理标志（blend_shade_enabled）来控制处理电路以结束当前软件程序，以产生输出数据，并根据软件处理标志触发输出数据的处理通过专用功能硬件或触发处理电路，以在输出数据上执行另外的软件程序以产生软件产生的结果数据，而不是由专用硬件电路产生的硬件产生的结果数据。

4. 发明授权

US08589934B2 Controlling priority levels of pending threads awaiting processing 有权
标题翻译：控制待处理线程的优先级等待处理
公开(公告)号：US08589934B2
公开(公告)日：2013-11-19
申请号：US13064598
申请日：2011-04-01
申请人： Nebojsa Makljenovic , Edvard Fielding , Andreas Engh-Halstvedt
发明人： Nebojsa Makljenovic , Edvard Fielding , Andreas Engh-Halstvedt
IPC分类号： G06F9/46
CPC分类号： G06F9/54 , G06F9/3851 , G06F9/3859 , G06F9/5011 , G06F2209/5021 , G06F2209/507
摘要： A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.
摘要翻译：数据处理装置包括处理电路，其布置成使用处理电路可访问的资源来处理处理线程。提供管线用于处理待处理电路等待处理的至少两个待处理线程。流水线包括至少一个资源请求流水线级，用于请求访问待处理线程的资源。优先级控制器控制待处理线程的优先级。优先权级别定义优先级，通过该优先级等待线程授予对资源的访问权限。当待处理线程达到最终流水线阶段时，如果请求资源不可用，则该线程的优先级级别被有选择地提升，并且该线程返回到流水线的第一流水线级。如果所请求的资源可用，则线程将从管道转发。

5. 发明申请

US20120293545A1 GRAPHICS PROCESSING SYSTEMS 有权
标题翻译：图形处理系统
公开(公告)号：US20120293545A1
公开(公告)日：2012-11-22
申请号：US13111658
申请日：2011-05-19
申请人： Andreas Engh-Halstvedt , Jorn Nystad , Edvard Sorgard , Frode Heggelund
发明人： Andreas Engh-Halstvedt , Jorn Nystad , Edvard Sorgard , Frode Heggelund
IPC分类号： G09G5/377 , G09G5/39
CPC分类号： G06T15/40 , G06F17/30265 , G06T3/4038 , G06T11/001 , G06T11/40 , G06T11/60 , G06T2210/62 , G09G5/14 , G09G5/39 , G09G5/393
摘要： In a tile-based graphics processing system, when an overlay image is to be rendered onto an existing image, the existing tile data for the existing image from the frame buffer in the main memory is pre-loaded into the local colour buffer of the graphics processor (step 41). The overlay content is then rendered and used to modify the tile data stored in the colour buffer (step 44). When the data for a given sampling position stored in the tile buffer is modified as a result of the overlay image, a corresponding dirty bit for the tile region that the sampling position falls within is set (step 45). Then, when all the rendering for the tile has been completed, the dirty bits are examined to determine which regions of the tile have been modified (step 46). The modified tile regions are written back to the output image in the frame buffer in the main memory (step 47), but any regions whose dirty bits have not been set are not written back to the frame buffer in the main memory.
摘要翻译：在基于瓦片的图形处理系统中，当将覆盖图像呈现到现有图像上时，来自主存储器中的帧缓冲器的现有图像的现有瓦片数据被预加载到图形的本地颜色缓冲器中处理器（步骤41）。覆盖内容然后被渲染并用于修改存储在彩色缓冲器中的瓦片数据（步骤44）。当存储在瓦片缓冲器中的给定采样位置的数据作为覆盖图像的结果被修改时，设置采样位置所在的瓦片区域的对应的脏位（步骤45）。然后，当瓦片的所有渲染已经完成时，检查脏位以确定瓦片的哪些区域已被修改（步骤46）。经修改的瓦片区域被写回到主存储器中的帧缓冲器中的输出图像（步骤47），但是没有设置脏位的任何区域都不会被写回到主存储器中的帧缓冲器。

6. 发明授权

US07996659B2 Microprocessor instruction that allows system routine calls and returns from all contexts 有权
标题翻译：允许系统例程调用和从所有上下文返回的微处理器指令
公开(公告)号：US07996659B2
公开(公告)日：2011-08-09
申请号：US11145613
申请日：2005-06-06
申请人： Erik K. Renno , Oyvind Strom , Andreas Engh-Halstvedt , Havard Skinnemoen
发明人： Erik K. Renno , Oyvind Strom , Andreas Engh-Halstvedt , Havard Skinnemoen
IPC分类号： G06F9/00
CPC分类号： G06F9/30181 , G06F9/30101 , G06F9/4486
摘要： An apparatus comprises register means for storing a return context upon initiation of a supervisor call instruction and restoring means to restore a privilege level and status register upon execution of a supervisor return instruction. The supervisor call instruction can be called from all contexts.
摘要翻译：一种装置，包括：登记装置，用于在启动监督程序调用指令时存储返回上下文;以及恢复装置，用于在执行管理程序返回指令时恢复特权级别和状态寄存器。可以从所有上下文调用主管调用指令。

7. 发明申请

US20070006200A1 Microprocessor instruction that allows system routine calls and returns from all contexts 有权
标题翻译：允许系统例程调用和从所有上下文返回的微处理器指令
公开(公告)号：US20070006200A1
公开(公告)日：2007-01-04
申请号：US11145613
申请日：2005-06-06
申请人： Erik Renno , Oyvind Strom , Andreas Engh-Halstvedt , Havard Skinnemoen
发明人： Erik Renno , Oyvind Strom , Andreas Engh-Halstvedt , Havard Skinnemoen
IPC分类号： G06F9/44
CPC分类号： G06F9/30181 , G06F9/30101 , G06F9/4486
摘要： An apparatus comprises register means for storing a return context upon initiation of a supervisor call instruction and restoring means to restore a privilege level and status register upon execution of a supervisor return instruction. The supervisor call instruction can be called from all contexts.
摘要翻译：一种装置，包括：登记装置，用于在启动监督程序调用指令时存储返回上下文;以及恢复装置，用于在执行管理程序返回指令时恢复特权级别和状态寄存器。可以从所有上下文调用主管调用指令。

8. 发明申请

US20070220334A1 Debugging system and method for use with software breakpoint 有权
标题翻译：用于软件断点的调试系统和方法
公开(公告)号：US20070220334A1
公开(公告)日：2007-09-20
申请号：US11354340
申请日：2006-02-14
申请人： Frode Pedersen , Andreas Engh-Halstvedt , Erik Renno , Are Arseth
发明人： Frode Pedersen , Andreas Engh-Halstvedt , Erik Renno , Are Arseth
IPC分类号： G06F11/00
CPC分类号： G06F11/2236 , G06F11/3648
摘要： Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from a non-debug mode upon executing a software breakpoint. The system may include a program memory configured to hold instructions for a program, where the software breakpoint replaces at least one of the instructions. The system may also include an instruction replacement register separate from the program memory that is configured to receive the replaced instruction from any of the processor and an external debugger. The system may further include a control component that controls whether the processor fetches a next instruction for execution from the program memory or from the instruction replacement register.
摘要翻译：提供了用于调试在处理器上执行的程序的方法和系统。在第一实现中，处理系统包括处理器，其被配置为在执行软件断点时从非调试模式切换到调试模式。该系统可以包括被配置为保存用于程序的指令的程序存储器，其中软件断点替换指令中的至少一个。系统还可以包括与程序存储器分离的指令替换寄存器，其被配置为从任何处理器和外部调试器接收替换的指令。该系统还可以包括控制组件，该控制组件控制处理器是否从程序存储器或从指令替换寄存器获取用于执行的下一个指令。

9. 发明授权

US09472018B2 Graphics processing systems 有权
标题翻译：图形处理系统
公开(公告)号：US09472018B2
公开(公告)日：2016-10-18
申请号：US13111658
申请日：2011-05-19
申请人： Andreas Engh-Halstvedt , Jorn Nystad , Edvard Sorgard , Frode Heggelund
发明人： Andreas Engh-Halstvedt , Jorn Nystad , Edvard Sorgard , Frode Heggelund
IPC分类号： G09G5/00 , G09G5/02 , G06F13/00 , G09G5/36 , G06K9/36 , G06K9/54 , G06T15/40 , G09G5/393 , G06T11/60 , G06T11/00 , G09G5/39 , G09G5/14 , G06T3/40 , G06F17/30
CPC分类号： G06T15/40 , G06F17/30265 , G06T3/4038 , G06T11/001 , G06T11/40 , G06T11/60 , G06T2210/62 , G09G5/14 , G09G5/39 , G09G5/393
摘要： In a tile-based graphics processing system, when an overlay image is to be rendered onto an existing image, the existing tile data for the existing image from the frame buffer in the main memory is pre-loaded into the local color buffer of the graphics processor (step 41). The overlay content is then rendered and used to modify the tile data stored in the color buffer (step 44). When the data for a given sampling position stored in the tile buffer is modified as a result of the overlay image, a corresponding dirty bit for the tile region that the sampling position falls within is set (step 45). Then, when all the rendering for the tile has been completed, the dirty bits are examined to determine which regions of the tile have been modified (step 46). The modified tile regions are written back to the output image in the frame buffer in the main memory (step 47), but any regions whose dirty bits have not been set are not written back to the frame buffer in the main memory.
摘要翻译：在基于瓦片的图形处理系统中，当将覆盖图像呈现到现有图像上时，来自主存储器中的帧缓冲器的现有图像的现有瓦片数据被预加载到图形的本地颜色缓冲器中处理器（步骤41）。覆盖内容然后被渲染并用于修改存储在彩色缓冲器中的瓦片数据（步骤44）。当存储在瓦片缓冲器中的给定采样位置的数据作为覆盖图像的结果被修改时，设置采样位置所在的瓦片区域的对应的脏位（步骤45）。然后，当瓦片的所有渲染已经完成时，检查脏位以确定瓦片的哪些区域已被修改（步骤46）。经修改的瓦片区域被写回到主存储器中的帧缓冲器中的输出图像（步骤47），但是没有设置脏位的任何区域都不会被写回到主存储器中的帧缓冲器。

10. 发明授权

US07506205B2 Debugging system and method for use with software breakpoint 有权
标题翻译：用于软件断点的调试系统和方法
公开(公告)号：US07506205B2
公开(公告)日：2009-03-17
申请号：US11354340
申请日：2006-02-14
申请人： Frode Milch Pedersen , Andreas Engh-Halstvedt , Erik Knutsen Renno , Are Arseth
发明人： Frode Milch Pedersen , Andreas Engh-Halstvedt , Erik Knutsen Renno , Are Arseth
IPC分类号： G06F11/00
CPC分类号： G06F11/2236 , G06F11/3648
摘要： Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from a non-debug mode upon executing a software breakpoint. The system may include a program memory configured to hold instructions for a program, where the software breakpoint replaces at least one of the instructions. The system may also include an instruction replacement register separate from the program memory that is configured to receive the replaced instruction from any of the processor and an external debugger. The system may further include a control component that controls whether the processor fetches a next instruction for execution from the program memory or from the instruction replacement register.
摘要翻译：提供了用于调试在处理器上执行的程序的方法和系统。在第一实现中，处理系统包括处理器，其被配置为在执行软件断点时从非调试模式切换到调试模式。该系统可以包括被配置为保存用于程序的指令的程序存储器，其中软件断点替换指令中的至少一个。系统还可以包括与程序存储器分离的指令替换寄存器，其被配置为从任何处理器和外部调试器接收替换的指令。该系统还可以包括控制组件，该控制组件控制处理器是否从程序存储器或从指令替换寄存器获取用于执行的下一个指令。

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