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1. 发明申请

US20060277396A1 Memory operations in microprocessors with multiple execution modes and register files 审中-公开
标题翻译：具有多种执行模式和寄存器文件的微处理器中的内存操作
公开(公告)号：US20060277396A1
公开(公告)日：2006-12-07
申请号：US11145770
申请日：2005-06-06
申请人： Erik Renno , Oyvind Strom
发明人： Erik Renno , Oyvind Strom
IPC分类号： G06F9/44
CPC分类号： G06F9/30101 , G06F9/30043
摘要： An apparatus and method for saving and operating on a register set, shadow register file, and memory is presented. A register within a register set that is associated with an active execution state in a computing system is used as an address pointer to a memory location. The content of the memory location is either loaded from memory into an identified shadow register, or the content of a shadow register is stored into the memory location. The operation is normally performed by executing a single instruction by a processor or by circuitry associated with a processor or computer system. Active and inactive execution states may be under the control of an operating system running on the processor or computer system.
摘要翻译：提出了一种用于保存和操作寄存器组，影子寄存器文件和存储器的装置和方法。使用与计算系统中的主动执行状态相关联的寄存器组内的寄存器作为到存储器位置的地址指针。存储器位置的内容从存储器加载到识别的影子寄存器中，或者将影子寄存器的内容存储到存储器位置。该操作通常由处理器或与处理器或计算机系统相关联的电路执行单个指令来执行。主动和非活动执行状态可能处于在处理器或计算机系统上运行的操作系统的控制之下。

2. 发明申请

US20060285593A1 System for increasing the speed of a sum-of-absolute-differences operation 有权
标题翻译：用于提高绝对差异和度运算速度的系统
公开(公告)号：US20060285593A1
公开(公告)日：2006-12-21
申请号：US11140749
申请日：2005-05-31
申请人： Ronny Pedersen , Erik Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik Renno , Oyvind Strom
IPC分类号： H04N11/02
CPC分类号： G06F7/544 , H04N19/43 , H04N19/51
摘要： An adaptation of the sum-of-absolute-differences (SAD) calculation is implemented by modifying existing circuitry in a microprocessor. The adaptation yields a reduction of over 30% for a current SAD calculation. The adaptation includes a first and second operand register, each storing respectively a first and second set of 2's complement binary data, an arithmetic logic unit (ALU), and a destination register. An add/subtract enable input on the ALU receives a most significant bit (MSB) of the second set of binary data. The ALU adds the first and second data sets if the MSB is a “0” and subtracts the second data set from the first data set if the MSB is a “1.” The add/subtract enable input has the effect of taking the absolute value of the second data set without having to first perform an absolute value determination, thus eliminating processing steps.
摘要翻译：通过修改微处理器中的现有电路来实现绝对差值（SAD）计算的适应。对于当前的SAD计算，适应性减少超过30％。适配包括第一和第二操作数寄存器，每个寄存器分别存储第二和第二组二进制补码二进制数据，算术逻辑单元（ALU）和目的地寄存器。 ALU上的加/减使能输入接收第二组二进制数据的最高有效位（MSB）。如果MSB为“0”，则ALU添加第一和第二数据集，并且如果MSB为“1”，则从第一数据集中减去第二数据集。加/减使能输入具有获取第二数据集的绝对值而不必首先执行绝对值确定的效果，从而消除处理步骤。

3. 发明申请

US20060277241A1 Apparatus and method for performing efficient multiply-accumulate operations in microprocessors 有权
标题翻译：在微处理器中执行有效的乘法累积运算的装置和方法
公开(公告)号：US20060277241A1
公开(公告)日：2006-12-07
申请号：US11142920
申请日：2005-06-01
申请人： Oyvind Strom , Erik Renno
发明人： Oyvind Strom , Erik Renno
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F7/5443 , G06F9/3001 , G06F9/30101 , G06F9/30138 , G06F9/3824 , G06F9/3838 , G06F9/3857 , G06F9/3859
摘要： An apparatus for performing multiply-accumulate operations in a microprocessor comprising operand input registers for receiving data to be operated on an adder and a multiplier for performing operations on the data, a result output port for presenting results to the microprocessor, a multiplexer for storing results, an accumulator cache for storing an accumulator value internal to the apparatus, and control circuitry for controlling the operation of the apparatus.
摘要翻译：一种用于在微处理器中执行多重累加操作的装置，包括操作数输入寄存器，用于接收在加法器上操作的数据和用于对数据执行操作的乘法器，用于向微处理器呈现结果的结果输出端口，用于存储结果的多路复用器用于存储装置内部的累加器值的累加器高速缓存器，以及用于控制装置的操作的控制电路。

4. 发明申请

US20060271763A1 Extracted-index addressing of byte-addressable memories 有权
标题翻译：字节寻址存储器的提取索引寻址
公开(公告)号：US20060271763A1
公开(公告)日：2006-11-30
申请号：US11140750
申请日：2005-05-31
申请人： Ronny Pedersen , Erik Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik Renno , Oyvind Strom
IPC分类号： G06F9/34
CPC分类号： G06F9/355 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A multiplexer has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control passes the specified byte to its output. The extracted byte is provided directly at specific bit positions of a zero-extended address offset word. The offset word is added to the base address, the sum being used to address memory contents that are loaded into the destination register.
摘要翻译：可用于可寻址寻址存储器的索引寻址的微处理器电路包括由指令指定的字长索引，基地址和目标寄存器。该指令还指定要提取的索引寄存器中打包的一个字节。多路复用器具有访问索引寄存器的所有字节的字宽输入端，并且响应于字节选择控制将指定的字节传递到其输出。提取的字节直接在零扩展地址偏移字的特定位位置处提供。偏移字被添加到基址中，该和用于寻址加载到目标寄存器中的存储器内容。

5. 发明申请

US20060236077A1 Microprocessor access of operand stack as a register file using native instructions 有权
标题翻译：使用本地指令将操作数堆栈的微处理器访问作为寄存器文件
公开(公告)号：US20060236077A1
公开(公告)日：2006-10-19
申请号：US11107235
申请日：2005-04-15
申请人： Oyvind Strom , Erik Renno , Kristian Monsen
发明人： Oyvind Strom , Erik Renno , Kristian Monsen
IPC分类号： G06F9/40
CPC分类号： G06F9/30134 , G06F9/3016 , G06F9/30196 , G06F9/321 , G06F9/3861
摘要： A combined native (RISC or CISC) microprocessor and stack (Java) machine are constructed so that Java VM instructions can be executed in hardware. Most Java instructions are executed directly, while more complex Java instructions, such as those manipulating Java objects, are executed as native microcode. In order for native microcode instructions to access the Java operand stack, a Java operand stack pointer points to the register file location that is the current top of the stack, while a remap bit in the status register indicates that registers specified in native instructions are remapped as the maximum Java operand stack pointer value minus the present value of the Java operand stack pointer.
摘要翻译：构建了一个组合的本机（RISC或CISC）微处理器和堆栈（Java）机器，以便可以在硬件中执行Java VM指令。大多数Java指令都是直接执行的，而更复杂的Java指令（如操作Java对象的Java指令）将作为本机微代码执行。为了使本地微代码指令访问Java操作数堆栈，Java操作数堆栈指针指向作为堆栈当前顶部的寄存器文件位置，而状态寄存器中的重映射位指示本机指令中指定的寄存器被重新映射作为最大Java操作数堆栈指针值减去Java操作数堆栈指针的当前值。

6. 发明申请

US20070006200A1 Microprocessor instruction that allows system routine calls and returns from all contexts 有权
标题翻译：允许系统例程调用和从所有上下文返回的微处理器指令
公开(公告)号：US20070006200A1
公开(公告)日：2007-01-04
申请号：US11145613
申请日：2005-06-06
申请人： Erik Renno , Oyvind Strom , Andreas Engh-Halstvedt , Havard Skinnemoen
发明人： Erik Renno , Oyvind Strom , Andreas Engh-Halstvedt , Havard Skinnemoen
IPC分类号： G06F9/44
CPC分类号： G06F9/30181 , G06F9/30101 , G06F9/4486
摘要： An apparatus comprises register means for storing a return context upon initiation of a supervisor call instruction and restoring means to restore a privilege level and status register upon execution of a supervisor return instruction. The supervisor call instruction can be called from all contexts.
摘要翻译：一种装置，包括：登记装置，用于在启动监督程序调用指令时存储返回上下文;以及恢复装置，用于在执行管理程序返回指令时恢复特权级别和状态寄存器。可以从所有上下文调用主管调用指令。

7. 发明申请

US20060277425A1 System and method for power saving in pipelined microprocessors 审中-公开
标题翻译：流水线微处理器节能的系统和方法
公开(公告)号：US20060277425A1
公开(公告)日：2006-12-07
申请号：US11146467
申请日：2005-06-07
申请人： Erik Renno , Oyvind Strom
发明人： Erik Renno , Oyvind Strom
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F9/30141 , G06F9/3824 , G06F9/3826
摘要： A system and method for preserving power in a microprocessor pipeline. The system includes a register file read control unit, the read control unit being configured to monitor one or more outputs from a control/decode unit of the pipeline and monitor write addresses from one or more other stages of the pipeline. The system also includes one or more read inhibit units each having an input, an output, and an enable terminal, the output of each of the one or more read inhibit units being coupled to a unique register port of a register file within the pipeline. The input of each of the one or more read inhibit units being coupled to the control/decode unit, and the enable terminal of each of the one or more read inhibit units being coupled to a unique output of the read control unit.
摘要翻译：一种用于在微处理器管道中保持功率的系统和方法。所述系统包括寄存器文件读取控制单元，所述读取控制单元被配置为监视来自所述流水线的控制/解码单元的一个或多个输出并且监视来自所述流水线的一个或多个其他阶段的写入地址。该系统还包括一个或多个读取禁止单元，每个读取禁止单元各自具有输入，输出和使能端，所述一个或多个禁止读取单元中的每一个的输出耦合到流水线内的寄存器文件的唯一寄存器端口。一个或多个禁止读取单元中的每一个的输入耦合到控制/解码单元，并且一个或多个禁止读取单元中的每一个的使能端耦合到读取控制单元的唯一输出。

8. 发明申请

US20070220334A1 Debugging system and method for use with software breakpoint 有权
标题翻译：用于软件断点的调试系统和方法
公开(公告)号：US20070220334A1
公开(公告)日：2007-09-20
申请号：US11354340
申请日：2006-02-14
申请人： Frode Pedersen , Andreas Engh-Halstvedt , Erik Renno , Are Arseth
发明人： Frode Pedersen , Andreas Engh-Halstvedt , Erik Renno , Are Arseth
IPC分类号： G06F11/00
CPC分类号： G06F11/2236 , G06F11/3648
摘要： Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from a non-debug mode upon executing a software breakpoint. The system may include a program memory configured to hold instructions for a program, where the software breakpoint replaces at least one of the instructions. The system may also include an instruction replacement register separate from the program memory that is configured to receive the replaced instruction from any of the processor and an external debugger. The system may further include a control component that controls whether the processor fetches a next instruction for execution from the program memory or from the instruction replacement register.
摘要翻译：提供了用于调试在处理器上执行的程序的方法和系统。在第一实现中，处理系统包括处理器，其被配置为在执行软件断点时从非调试模式切换到调试模式。该系统可以包括被配置为保存用于程序的指令的程序存储器，其中软件断点替换指令中的至少一个。系统还可以包括与程序存储器分离的指令替换寄存器，其被配置为从任何处理器和外部调试器接收替换的指令。该系统还可以包括控制组件，该控制组件控制处理器是否从程序存储器或从指令替换寄存器获取用于执行的下一个指令。

9. 发明申请

US20070192396A1 Packed add-subtract operation in a microprocessor 有权
标题翻译：在微处理器中进行加减法操作
公开(公告)号：US20070192396A1
公开(公告)日：2007-08-16
申请号：US11352711
申请日：2006-02-13
申请人： Ronny Pedersen , Erik Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik Renno , Oyvind Strom
IPC分类号： G06F7/42 , G06F9/44
CPC分类号： G06F7/505 , G06F7/49921 , G06F9/30014 , G06F9/30036 , G06F9/3885 , G06F17/142 , G06F2207/382
摘要： A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.
摘要翻译：一个微处理器的加字和减法操作由微处理器并行地由从寄存器文件的指定的源寄存器的指定的顶部或底部的半字位置获得的半字操作数并行，并且这些操作的和和差分结果被打包分配到指定目的地寄存器的相应顶部和底部半字位置。微处理器包括具有加法器电路的加法器电路的算术逻辑单元（ALU），其可选择性地分成独立的可选择的半字加法器，以对所选择的半字操作数执行加法运算或减法运算。 ALU的半字加法器通过一组多路复用器从源寄存器访问操作数，这些复用器在顶部和底部的半字位置之间进行选择。还可以提供对和差和差异结果的减半和饱和度修改的操作。

10. 发明申请

US20060282821A1 Efficient subprogram return in microprocessors 审中-公开
标题翻译：微处理器中有效的子程序返回
公开(公告)号：US20060282821A1
公开(公告)日：2006-12-14
申请号：US11149611
申请日：2005-06-10
申请人： Erik Renno , Oyvind Strom , Morten Lund
发明人： Erik Renno , Oyvind Strom , Morten Lund
IPC分类号： G06F9/44
CPC分类号： G06F9/30072 , G06F9/30054 , G06F9/30094 , G06F9/3806
摘要： A method and medium for performing subroutine return operations. Test operations are performed in parallel with other operations in a return operation. These test operations and the return operations are performed in response to a single instruction.
摘要翻译：用于执行子程序返回操作的方法和介质。在返回操作中与其他操作并行执行测试操作。这些测试操作和返回操作是响应于单个指令执行的。

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