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1. 发明授权

US08224638B1 Managing programmable device configuration 有权
标题翻译：管理可编程器件配置
公开(公告)号：US08224638B1
公开(公告)日：2012-07-17
申请号：US11650176
申请日：2007-01-05
申请人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
发明人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F2213/0038
摘要： A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
摘要翻译：管理可编程设备配置的方法可以包括在可编程设备内运行服务器配置图像并将不同的配置图像存储在与可编程设备通信地链接的非易失性存储器中。响应于通过通信链路从客户端发送到可编程设备的切换请求，可以将不同的配置图像加载到可编程设备中。

2. 发明授权

US07184946B2 Co-simulation via boundary scan interface 有权
标题翻译：通过边界扫描界面进行协同仿真
公开(公告)号：US07184946B2
公开(公告)日：2007-02-27
申请号：US10600885
申请日：2003-06-19
申请人： Jonathan B. Ballagh , Nabeel Shirazi , Christopher N. Battson , Michael E. Darnall , Bradley K. Fross
发明人： Jonathan B. Ballagh , Nabeel Shirazi , Christopher N. Battson , Michael E. Darnall , Bradley K. Fross
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.
摘要翻译：将高级建模系统（HLMS）与用于协同仿真的可重配置硬件平台进行接口的方法和装置。在一个实施例中，边界扫描接口耦合到HLMS并且被配置为将HLMS发出的命令转换为大体上符合边界扫描协议的信号，并且将通常符合边界扫描协议的信号转换为与HLMS兼容的数据。为了配置硬件平台，实现了一个翻译器和一个包装器。翻译器在通常符合边界扫描协议的信号和符合第二协议的信号之间进行翻译。要在共模拟的组件在包装器中实例化，并且包装器在转换器和组件之间传送信号。

3. 发明授权

US08620638B1 Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design 有权
标题翻译：执行被测设计的仿真的方法和用于实现电路设计测试的电路
公开(公告)号：US08620638B1
公开(公告)日：2013-12-31
申请号：US12335025
申请日：2008-12-15
申请人： Chi Bun Chan , Jingzhao Ou , Shay Ping Seng , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Shay Ping Seng , Nabeel Shirazi
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5022
摘要： A method of performing a simulation of a design under test is disclosed. The method comprises implementing an input block having an adjustable output width; coupling test data to the input block; generating an input signal comprising the test data for the design under test according to an input requirement for the design under test by way of the input block; implementing an output block having an adjustable input width for receiving data from an output of the design under test; and coupling the output of the design under test to the output block according to an output requirement of the design under test. A circuit for enabling testing of a circuit design implemented in an integrated circuit is also disclosed.
摘要翻译：公开了一种对被测设计进行仿真的方法。该方法包括实现具有可调输出宽度的输入块; 将测试数据耦合到输入块; 根据输入块的被测设计的输入要求，生成包含被测设计的测试数据的输入信号; 实现具有可调输入宽度的输出块，用于从被测设计的输出接收数据; 并根据被测设计的输出要求将被测设计的输出耦合到输出块。还公开了一种能够测试在集成电路中实现的电路设计的电路。

4. 发明授权

US08600722B1 Method and apparatus for providing program-based hardware co-simulation of a circuit design 有权
标题翻译：用于提供电路设计的基于程序的硬件协同仿真的方法和装置
公开(公告)号：US08600722B1
公开(公告)日：2013-12-03
申请号：US11805133
申请日：2007-05-22
申请人： Chi Bun Chan , Nabeel Shirazi , Shay Ping Seng , Haibing Ma
发明人： Chi Bun Chan , Nabeel Shirazi , Shay Ping Seng , Haibing Ma
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： A method and apparatus for providing a program-based hardware co-simulation of a circuit design are described. In one example, a circuit design is implemented for programmable logic to establish a design under test (DUT). A co-simulation model is programmatically generated using primitives defined by an application programming interface (API). The circuit design is simulated by configuring the programmable logic with the DUT and driving a co-simulation engine to communicate with the DUT via execution of the co-simulation model.
摘要翻译：描述了一种用于提供电路设计的基于程序的硬件协同仿真的方法和装置。在一个示例中，实现用于可编程逻辑以建立被测设计（DUT）的电路设计。使用由应用程序编程接口（API）定义的原语以编程方式生成协同仿真模型。通过使用DUT配置可编程逻辑来模拟电路设计，并通过执行协同仿真模型驱动协同仿真引擎与DUT进行通信。

5. 发明授权

US07383478B1 Wireless dynamic boundary-scan topologies for field 有权
标题翻译：无线动态边界扫描拓扑领域
公开(公告)号：US07383478B1
公开(公告)日：2008-06-03
申请号：US11185118
申请日：2005-07-20
申请人： Jonathan B. Ballagh , Alexander Carreira , L. James Hwang , Roger B. Milne , Shay Ping Seng , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Alexander Carreira , L. James Hwang , Roger B. Milne , Shay Ping Seng , Nabeel Shirazi
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/3025 , G01R31/318572 , H04W4/18 , H04W24/00 , H04W92/00
摘要： A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.
摘要翻译：具有JTAG端口（例如FPGA）的可编程逻辑器件（PLD）提供有无线JTAG适配器以实现无线通信。与无线到JTAG适配器连接的多个PLD可以在网络中无线链接以形成大型边界扫描链串行接口。为了与具有无线JTAG端口的PLD通信，运行应用软件的主机PC还配备有无线收发器。

6. 发明授权

US07636653B1 Point-to-point ethernet hardware co-simulation interface 有权
标题翻译：点到点以太网硬件协同仿真界面
公开(公告)号：US07636653B1
公开(公告)日：2009-12-22
申请号：US11343367
申请日：2006-01-31
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5027
摘要： An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.
摘要翻译：与可编程设备上的基于软件的仿真工具和被测设计一起使用的以太网协同仿真界面可以包括主机接口和网络处理器。主机接口可以在主机计算系统上执行，并促进基于软件的仿真工具与被测设计的通信链路之间的数据传输。网络处理器可以在可编程设备内部实现，并促进通信链路和被测设计之间的数据传输。主机接口和网络处理器可以通过点对点以太网连接交换格式化为原始以太网帧的模拟数据。

7. 发明授权

US07747423B1 Systems and methods of co-simulation utilizing multiple PLDs in a boundary scan chain 有权
标题翻译：在边界扫描链中利用多个PLD进行协同仿真的系统和方法
公开(公告)号：US07747423B1
公开(公告)日：2010-06-29
申请号：US11527841
申请日：2006-09-27
申请人： Nabeel Shirazi , Jonathan B. Ballagh , Chi Bun Chan
发明人： Nabeel Shirazi , Jonathan B. Ballagh , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.
摘要翻译：使用耦合在一起以形成边界扫描链的多个可编程逻辑器件（PLD）执行分割电路设计的协同仿真的系统和方法。主机通过编程电缆耦合到扫描链。主计算机上的驻留是与电路设计中的块对应的运行时协同仿真块，其中每个块被指定为在扫描链中的一个PLD上运行; 与编程电缆接口的编程电缆设备驱动器; 和代理组件。代理组件耦合到所有运行时协同仿真模块和编程电缆设备驱动程序。每个共模拟块包括唯一的模式标识符，其也存在于相关联的PLD中。使用此模式标识符，可以从扫描链中提取针对特定PLD的数据和命令，同时忽略针对扫描链中其他PLD的数据和命令。

8. 发明授权

US07707019B1 Command buffering for hardware co-simulation 有权
标题翻译：用于硬件协同仿真的命令缓冲
公开(公告)号：US07707019B1
公开(公告)日：2010-04-27
申请号：US11234529
申请日：2005-09-23
申请人： Jonathan B. Ballagh , Chi Bun Chan , Nabeel Shirazi , Roger B. Milne
发明人： Jonathan B. Ballagh , Chi Bun Chan , Nabeel Shirazi , Roger B. Milne
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.
摘要翻译：涉及高级建模系统和诸如可编程逻辑器件（PLD）的集成电路的协同仿真的方法可以包括在写入PLD的至少一个输入端口时存储来自协同仿真引擎，并且响应于发送条件，将多个命令作为单个事务发送到PLD。当从PLD的至少一个输出端口读取时，根据高速缓存一致性的状态选择性地从PLD外部的高速缓存或PLD的存储器读取。

9. 发明授权

US08812289B1 Simulation that transfers port values of a design block via a configuration block of a programmable device 有权
标题翻译：模拟通过可编程设备的配置块传输设计块的端口值
公开(公告)号：US08812289B1
公开(公告)日：2014-08-19
申请号：US11732642
申请日：2007-04-04
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： G06F9/455 , G06F17/50 , G06F11/36 , G06F17/22 , G06F11/267
CPC分类号： G06F17/5027 , G06F9/455 , G06F11/267 , G06F11/3652 , G06F17/22 , G06F17/5009 , G06F2217/86
摘要： Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.
摘要翻译：模拟电子系统的方法。在一种方法中，软件协同仿真平台被配置为产生电子系统的设计块的多个输入端口的值的第一时间序列，消耗电子系统的多个输出端口的值的第二时间序列并且生成用于传送第一和第二序列值的访问事务。软件协同仿真平台生成用于传送用于设计块的重新配置数据的多个重配置事务。 PLD被配置为实现通信块和控制块。通信块从软件协同仿真平台接收重新配置和访问事务，并且控制块响应于重新配置事务重新配置PLD的可编程逻辑和互连资源。响应于访问事务，控制块还控制设计块的仿真。

10. 发明授权

US07590137B1 Parameterizable compact network processor for low-level communication with an integrated circuit 有权
标题翻译：可配置的紧凑型网络处理器，用于与集成电路进行低级通信
公开(公告)号：US07590137B1
公开(公告)日：2009-09-15
申请号：US11285708
申请日：2005-11-22
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： H04J3/24
CPC分类号： G06F13/385 , G06F2213/3808
摘要： A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.
摘要翻译：设置在集成电路上的网络处理器可以包括具有双端口块随机存取存储器的入口单元和具有双端口块随机存取存储器的出口单元。网络处理器还可以包括被配置为将分组化数据写入入口单元并从出口单元读取分组化数据的网络接口以及配置为协调网络接口，入口单元和出口之间的数据移动的协调处理器单元。

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