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1. 发明授权

US06319775B1 Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device 有权
标题翻译：用于在2位EEPROM器件中制造ONO浮栅电极的氮化工艺
公开(公告)号：US06319775B1
公开(公告)日：2001-11-20
申请号：US09433037
申请日：1999-10-25
申请人： Arvind Halliyal , Robert B. Ogle , Susan G. Kim , Kenneth Au
发明人： Arvind Halliyal , Robert B. Ogle , Susan G. Kim , Kenneth Au
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/3144 , H01L29/66833
摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a nitrogenated top oxide layer. The process includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. After forming the top oxide layer, an annealing process is carried out to diffuse nitrogen into the top oxide layer. The formation of a nitrogenated top oxide layer provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.
摘要翻译：在2位EEPROM器件中制造ONO浮栅电极的工艺包括形成氮化的顶部氧化物层。该方法包括使用原位LPCVD或RTCVD沉积工艺顺序地形成氮化硅层和顶部氧化物层，其中氮化硅层在形成顶部氧化物层之前不暴露于环境大气。在形成顶部氧化物层之后，进行退火处理以将氮扩散到顶部氧化物层中。氮化顶部氧化物层的形成通过减少ONO浮栅电极中的电荷泄漏来提供改进的两位EEPROM存储器件。

2. 发明授权

US06265268B1 High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device 有权
标题翻译：用于在两位EEPROM器件中制造ONO浮栅电极的高温氧化物沉积工艺
公开(公告)号：US06265268B1
公开(公告)日：2001-07-24
申请号：US09426672
申请日：1999-10-25
申请人： Arvind Halliyal , Robert B. Ogle , Hideki Komori , Kenneth Au
发明人： Arvind Halliyal , Robert B. Ogle , Hideki Komori , Kenneth Au
IPC分类号： H01L218247
CPC分类号： H01L29/7923 , H01L21/28282
摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a top oxide layer using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. by either an LPCVD or RTCVD deposition processor. The process further includes the sequential formation of a silicon nitride layer and a top oxide layer using an in-situ LPCVD or RTCVD deposition process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the top oxide layer using an HTO deposition process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.
摘要翻译：用于在2位EEPROM器件中制造ONO浮栅电极的工艺包括使用高温氧化物（HTO）沉积工艺形成顶部氧化物层，其中HTO工艺在约通过LPCVD或RTCVD沉积处理器700至约800℃。该方法还包括使用原位LPCVD或RTCVD沉积工艺顺序地形成氮化硅层和顶部氧化物层，其中氮化硅层在形成顶部氧化物层之前不暴露于环境大气中。使用HTO沉积工艺形成顶部氧化物层通过减少ONO浮栅电极中的电荷泄漏来提供改进的两位EEPROM存储器件。

3. 发明授权

US06180538B2 Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition 失效
标题翻译：在使用快速热化学气相沉积的2位EEPROM器件中制造ONO浮栅电极的工艺
公开(公告)号：US06180538B2
公开(公告)日：2001-01-30
申请号：US09426240
申请日：1999-10-25
申请人： Arvind Halliyal , Robert B. Ogle , Kenneth Au , Steven K. Park
发明人： Arvind Halliyal , Robert B. Ogle , Kenneth Au , Steven K. Park
IPC分类号： H01L2131
CPC分类号： H01L29/7923 , H01L21/28282 , H01L21/3143
摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a first and second oxide layers using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. The process further includes the sequential formation of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer using an RTCVD process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the first and second oxide layers using an RTCVD process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.
摘要翻译：用于在2位EEPROM器件中制造ONO浮栅电极的工艺包括使用高温氧化物（HTO）沉积工艺形成第一和第二氧化物层，其中HTO工艺在温度约700至约800℃。该方法还包括使用其中氮化硅层不暴露于环境大气的RTCVD工艺来顺序地形成第一氧化硅层，氮化硅层和第二氧化硅层在形成顶部氧化物层之前。使用RTCVD工艺形成第一和第二氧化物层通过减少ONO浮栅电极中的电荷泄漏来提供改进的两位EEPROM存储器件。

4. 发明授权

US06992370B1 Memory cell structure having nitride layer with reduced charge loss and method for fabricating same 有权
标题翻译：具有具有降低的电荷损失的氮化物层的存储单元结构及其制造方法
公开(公告)号：US06992370B1
公开(公告)日：2006-01-31
申请号：US10655179
申请日：2003-09-04
申请人： George J. Kluth , Robert B. Clark-Phelps , Joong S. Jeon , Huicai Zhong , Arvind Halliyal , Mark T. Ramsbey , Robert B. Ogle, Jr. , Kuo T. Chang , Wenmei Li
发明人： George J. Kluth , Robert B. Clark-Phelps , Joong S. Jeon , Huicai Zhong , Arvind Halliyal , Mark T. Ramsbey , Robert B. Ogle, Jr. , Kuo T. Chang , Wenmei Li
IPC分类号： H01L23/58 , H01L21/302
CPC分类号： H01L21/28282 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.
摘要翻译：根据一个实施例，存储单元结构包括半导体衬底，位于半导体衬底上的第一氧化硅层，位于第一氧化硅层之上的电荷存储层，位于电荷存储层上方的第二氧化硅层，以及位于所述第二氧化硅层上方的栅极层。在示例性实施例中，电荷存储层包括具有降低的氢含量的氮化硅，例如在约0至0.5原子百分比的范围内。结果，降低的氢含量降低了电荷存储层中的电荷损失。电荷存储层中的减少的电荷损失有利于减少存储器件中的阈值电压偏移，编程数据丢失和编程能力损失，从而提高存储器件性能。

5. 发明授权

US06645882B1 Preparation of composite high-K/standard-K dielectrics for semiconductor devices 有权
标题翻译：制备用于半导体器件的复合高K /标准K电介质
公开(公告)号：US06645882B1
公开(公告)日：2003-11-11
申请号：US10051790
申请日：2002-01-17
申请人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
发明人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
IPC分类号： H01L21469
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/316 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a first dielectric material and a second dielectric material to form a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and annealing the layered dielectric structure at an elevated temperature to form a composite dielectric layer.
摘要翻译：一种半导体器件和制造具有复合介电层的半导体器件的方法，包括提供半导体衬底的步骤; 在所述半导体衬底上沉积交替的第一电介质材料和第二介电材料的子层，以形成具有至少两个第二电介质材料和所述第二电介质材料中的至少一个的子层的层状电介质结构，其中一个所述第一电介质材料和所述第二电介质材料是高K电介质材料，所述第一电介质材料和所述第二电介质材料中的另一个是包含氧化铝的标准K电介质材料; 以及在升高的温度下退火所述层状电介质结构以形成复合介电层。

6. 发明授权

US06306777B1 Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming 有权
标题翻译：闪存，其具有设置在间隔电介质结构和形成方法之间的处理层
公开(公告)号：US06306777B1
公开(公告)日：2001-10-23
申请号：US09595166
申请日：2000-06-15
申请人： Robert B. Ogle, Jr. , Arvind Halliyal
发明人： Robert B. Ogle, Jr. , Arvind Halliyal
IPC分类号： H01L218247
CPC分类号： H01L21/28273 , H01L29/511
摘要： A flash memory structure and fabrication process whereby stacks of a first poly-crystalline or of an amorphous silicon material (polysilicon), having a bottom layer member of an interpoly dielectric stack, are processed for formation of a post-treatment layer over the bottom interpoly dielectric layer member. The post-treatment layer is essentially a solid material formed by a chemical reaction for purposes of improving the reliability of an interpoly dielectric stack and results in changes to the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The post-treatment layer is formed by exposing the polysilicon stacks with the bottom interpoly dielectric layer member to a selected one of at least three ambient reagent gases. The selected ambient reagent gases and exposure of the semiconductor structure being performed in either a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber. Then at least three ambient reagent gases are selected from a group of reagent gases consisting essentially of N2O/NO, O2/H2O/O3, and NH3/N2. Any of the ambient reagent gases may be selected and utilized in a selected fabrication tools for pre-treating the surface of the bottom interpoly dielectric stack member prior to forming the complete interpoly dielectric stack of the flash memory element. The subsequently formed interpoly dielectric stack being a modified ONO stack where the post-treatment layer is disposed between the bottom silicon dioxide layer and the silicon nitride and silicon dioxide layers.
摘要翻译：闪存结构和制造工艺，其中处理具有多层电介质堆叠的底层构件的第一多晶体或非晶硅材料（多晶硅）的堆叠，以在底部间隔层上形成后处理层电介质层构件。后处理层基本上是通过化学反应形成的固体材料，目的是改善多聚电介质堆叠的可靠性，并导致闪速存储元件的电容器耦合比的变化，并允许使用新的电源和编程电压。后处理层通过将具有底部间隔电介质层构件的多晶硅堆叠暴露于至少三种环境试剂气体中选定的一种来形成。选择的环境试剂气体和半导体结构的暴露在分批炉，单晶片快速热退火工具或等离子体室中进行。然后，从基本上由N 2 O / NO，O 2 / H 2 O / O 3和NH 3 / N 2组成的一组试剂气体中选择至少三种环境试剂气体。可以在选择的制造工具中选择和使用任何环境试剂气体，以在形成闪速存储元件的完整的多余介电叠层之前预处理底部多聚电介质堆叠构件的表面。随后形成的互间电介质叠层是修饰的ONO叠层，其中后处理层设置在底部二氧化硅层和氮化硅和二氧化硅层之间。

7. 发明授权

US06849925B1 Preparation of composite high-K/standard-K dielectrics for semiconductor devices 失效
标题翻译：制备用于半导体器件的复合高K /标准K电介质
公开(公告)号：US06849925B1
公开(公告)日：2005-02-01
申请号：US10656470
申请日：2003-09-05
申请人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
发明人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
IPC分类号： H01L21/28 , H01L21/316 , H01L29/51 , H01L23/58
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/316 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a composite dielectric layer, including a semiconductor substrate, alternating sub-layers including a first dielectric material and a second dielectric material on the semiconductor substrate, the sub-layers forming a composite dielectric layer having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and the composite dielectric layer includes a reaction product of the high-K dielectric material and the standard-K dielectric material. In one embodiment, the composite dielectric layer includes a substantially uniform layer of the reaction product of the first dielectric material and the second dielectric material.
摘要翻译：一种具有复合电介质层的半导体器件，包括半导体衬底，在半导体衬底上包括第一电介质材料和第二电介质的交替子层，所述子层形成具有至少两个子层的复合电介质层第一介电材料和第二电介质材料中的至少一个，其中第一电介质材料和第二电介质材料之一是高K电介质材料，第一电介质材料和第二电介质材料中的另一个是标准 -K介电材料，包括氧化铝; 并且复合介电层包括高K介电材料和标准K电介质材料的反应产物。在一个实施例中，复合介电层包括第一电介质材料和第二电介质材料的反应产物的基本均匀的层。

8. 发明授权

US07001814B1 Laser thermal annealing methods for flash memory devices 失效
标题翻译：闪存器件的激光热退火方法
公开(公告)号：US07001814B1
公开(公告)日：2006-02-21
申请号：US10438942
申请日：2003-05-16
申请人： Arvind Halliyal , Mark T. Ramsbey , Robert B. Ogle
发明人： Arvind Halliyal , Mark T. Ramsbey , Robert B. Ogle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/3144
摘要： A method of manufacturing an ONO (oxide-nitride-oxide) insulating layer for a flash memory device, the insulating layer including a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein at least one of the first oxide layer, the nitride layer and the second oxide layer are conditioned using laser thermal annealing.
摘要翻译：一种制造闪存器件的ONO（氧化物 - 氮化物 - 氧化物）绝缘层的方法，所述绝缘层包括第一氧化物层，所述第一氧化物层上的氮化物层和所述氮化物层上的第二氧化物层，其中使用激光热退火来调节第一氧化物层，氮化物层和第二氧化物层中的至少一个。

9. 发明授权

US06858496B1 Oxidizing pretreatment of ONO layer for flash memory 有权
标题翻译：用于闪存的ONO层的氧化预处理
公开(公告)号：US06858496B1
公开(公告)日：2005-02-22
申请号：US10010280
申请日：2001-12-05
申请人： Robert B. Ogle , Arvind Halliyal
发明人： Robert B. Ogle , Arvind Halliyal
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762
CPC分类号： H01L21/28273
摘要： A method of forming a dielectric structure for a flash memory cell includes forming a first layer of silicon dioxide, forming a layer of silicon nitride on the first layer of silicon dioxide, and pretreating the silicon nitride layer. Pretreatment of the silicon nitride layer includes oxidation. The method further includes depositing a second layer of silicon dioxide on the pretreated silicon nitride layer. Oxidation of the silicon nitride can occur in a batch process or in a single wafer tool, such as a single wafer rapid thermal anneal (RTA) tool. The oxidizing pretreatment of the nitride layer improves the integrity of the ONO structure and enables the second layer of silicon dioxide to be deposited rather than thermally grown. Because the nitride layer undergoes less change after deposition of the second layer of silicon dioxide, the present method improves the overall reliability of the ONO structure.
摘要翻译：形成闪存单元的电介质结构的方法包括：形成第一层二氧化硅，在第一层二氧化硅上形成氮化硅层，并预处理氮化硅层。氮化硅层的预处理包括氧化。该方法还包括在预处理的氮化硅层上沉积第二层二氧化硅。氮化硅的氧化可以在间歇工艺中或单个晶片工具（例如单晶片快速热退火（RTA））工具中进行。氮化物层的氧化预处理改善了ONO结构的完整性，并且能够沉积第二层二氧化硅而不是热生长。因为在第二层二氧化硅沉积之后氮化物层经历较少的变化，所以本方法提高了ONO结构的整体可靠性。

10. 发明授权

US06674138B1 Use of high-k dielectric materials in modified ONO structure for semiconductor devices 有权
标题翻译：用于半导体器件的改性ONO结构中的高k电介质材料
公开(公告)号：US06674138B1
公开(公告)日：2004-01-06
申请号：US10036757
申请日：2001-12-31
申请人： Arvind Halliyal , Mark T. Ramsbey , Kuo-Tung Chang , Nicholas H. Tripsas , Robert B. Ogle
发明人： Arvind Halliyal , Mark T. Ramsbey , Kuo-Tung Chang , Nicholas H. Tripsas , Robert B. Ogle
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66833 , H01L29/7923
摘要： A process for fabrication of a semiconductor device including a modified ONO structure, including forming the modified ONO structure by providing a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; depositing a layer comprising a high-K dielectric material on the first oxide layer; and forming a top oxide layer on the layer comprising a high-K dielectric material. The semiconductor device may be, e.g., a MIRRORBIT™ two-bit EEPROM device or a floating gate flash device including a modified ONO structure.
摘要翻译：一种制造包括改性ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一氧化物层; 在所述第一氧化物层上沉积包含高K电介质材料的层; 以及在包含高K电介质材料的层上形成顶部氧化物层。半导体器件可以是例如MIRRORBIT TM 2位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。

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