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1. 发明授权

US4707834A Computer-based instrument system 失效
标题翻译：基于计算机的仪器系统
公开(公告)号：US4707834A
公开(公告)日：1987-11-17
申请号：US777104
申请日：1985-09-17
申请人： Arnold M. Frisch , Allen L. Hollister , Larry L. Hutchinson
发明人： Arnold M. Frisch , Allen L. Hollister , Larry L. Hutchinson
IPC分类号： G05B15/02 , G01R31/319 , G06F13/38 , G06F15/16 , G06F15/173 , G06F11/00
CPC分类号： G01R31/31922 , G01R31/31907 , G01R31/31908 , G06F13/385
摘要： A computer-based instrument system is provided for progammably configuring a variety of computer-based test instruments for performing a variety of tests and permitting high speed execution of tests through concurrent operation of individual test instruments. The instruments are implemented on circuit boards and mounted in a chassis including permanent backplane wiring interconnecting the instruments and a timing and triggering control unit. The backplane wiring includes a conventional computer bus for carrying instructions from a master controller to each instrument and lines for a common system clock signal, protocol signals, and trigger signals between selected instruments and the timing and triggering control unit for synchronizing the operation of the instruments when performing a test. The timing and triggering control unit is adapted to programmably control instrument triggering according to individual test requirements without modification of backplane wiring. The backplane wiring further includes a high speed data bus for rapidly transferring data between instruments in the course of a test.
摘要翻译：提供了一种基于计算机的仪器系统，用于可程式地配置各种基于计算机的测试仪器，用于执行各种测试，并允许通过单独测试仪器的并发操作高速执行测试。这些仪器在电路板上实现，并安装在底盘中，其中包括连接仪器的永久背板布线和定时和触发控制单元。背板布线包括用于承载来自主控制器到每个仪器的指令的常规计算机总线，以及用于公共系统时钟信号，协议信号和所选择的仪器之间的触发信号的线路以及用于使仪器的操作同步的定时和触发控制单元进行测试时。定时和触发控制单元适用于可编程控制根据单独测试要求的仪器触发，而无需修改背板接线。背板布线还包括用于在测试过程中在仪器之间快速传输数据的高速数据总线。

2. 发明授权

US07219269B2 Self-calibrating strobe signal generator 失效
标题翻译：自校准选通信号发生器
公开(公告)号：US07219269B2
公开(公告)日：2007-05-15
申请号：US10628995
申请日：2003-07-28
申请人： Arnold M. Frisch
发明人： Arnold M. Frisch
IPC分类号： G01R31/28 , G04F10/00 , G04F8/00
CPC分类号： G01R31/3191 , G01R31/3187 , G01R31/31937
摘要： A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by a target delay specified by input data. The strobe signal generator includes a multiplexer, a delay circuit and a controller. The multiplexer normally provides the input strobe signal as a multiplexer output signal to the delay circuit which generates edges in each of the first and second strobe signals in response to each edge in the multiplexer output signal with a programmable delay between corresponding first and second strobe signal edges. During a calibration process the control circuit adjusts the programmable delay by counting cycles of a reference clock signal occurring during a predetermined number of cycles of the multiplexer output signal when the multiplexer is set to select the first strobe signal and then the second strobe signal as the source of the multiplexer output signal such that the multiplexer output signal oscillates, and by incrementing or decrementing the programmable delay depending on whether a difference between the counts matches the input data.
摘要翻译：用于BIST电路的自校准选通信号发生器通过产生在时间上由输入数据指定的目标延迟的第一和第二选通信号的相应边缘来响应输入选通信号的边沿。选通信号发生器包括多路复用器，延迟电路和控制器。复用器通常将输入选通信号作为多路复用器输出信号提供给延迟电路，该延迟电路响应于多路复用器输出信号中的每个边沿，在相应的第一和第二选通信号之间具有可编程延迟，从而产生第一和第二选通信号中的每一个中的边沿边缘。在校准过程期间，当多路复用器被设置为选择第一选通信号，然后第二选通信号作为第二选通信号时，控制电路通过计数在多路复用器输出信号的预定次数周期期间出现的基准时钟信号的周期来调整可编程延迟多路复用器输出信号的源，使得多路复用器输出信号振荡，并且通过根据计数之间的差是否与输入数据匹配来递增或递减可编程延迟。

3. 发明授权

US4952820A Reduction of intermodulation distortion in light emitting diodes 失效
标题翻译：降低发光二极管中的互调失真
公开(公告)号：US4952820A
公开(公告)日：1990-08-28
申请号：US329052
申请日：1989-03-27
申请人： Arnold M. Frisch
发明人： Arnold M. Frisch
IPC分类号： H01L33/00 , H01S5/042 , H05B33/08
CPC分类号： H05B33/0803
摘要： A low distortion light source comprising a light emitting diode and a compensating diode connected in parallel with respect to a D.C. bias current and in anti-series with respect to an A.C. signal source. The compensating diode is selected to have a forward resistance similar to the forward resistance of the LED. Adjusting the D.C. bias current through the diodes to be approximately equal matches the forward resistance characteristics and substantially reduces the undesired intermodulation products.

4. 发明授权

US07389449B2 Edge selecting triggering circuit 失效
标题翻译：边沿选择触发电路
公开(公告)号：US07389449B2
公开(公告)日：2008-06-17
申请号：US11069879
申请日：2005-02-28
申请人： Thomas Arthur Almy , Arnold M. Frisch
发明人： Thomas Arthur Almy , Arnold M. Frisch
IPC分类号： G11B5/00 , G11B20/20 , G06K5/04
CPC分类号： G01R31/3191 , G01R31/31932 , G06F11/263
摘要： A triggering circuit asserts a trigger signal in response to edges of a digital signal conveying a repetitive pattern of edges. The triggering circuit generates first data having a value identifying a position within the pattern of a last occurring edge of the digital signal and generates second data having a value identifying a position of a particular edge within the pattern that is to initiate a next assertion of the trigger signal. The triggering circuit asserts the trigger signal when the first and second data values match and de-asserts the trigger signal when the first and second data do not match. In a repetitive mode of operation, the triggering circuit keeps the second data value constant so that it always asserts the trigger signal in response to the same edge of the pattern. In a sequential mode of operation, the triggering circuit changes the value of the second data each time it asserts the trigger signal so that successive assertions of the trigger signal occur in response to differing edges of the digital signal pattern.
摘要翻译：触发电路响应于传送重复的边缘图案的数字信号的边缘而断言触发信号。所述触发电路产生具有标识所述数字信号的最后出现边缘的模式内的位置的值的第一数据，并且生成第二数据，所述第二数据具有标识所述模式内的特定边缘的位置的值，所述特定边缘的位置将起始下一个所述触发信号。当第一和第二数据值不匹配时，触发电路断言触发信号，并且当第一和第二数据不匹配时，触发电路解除触发信号。在重复的操作模式中，触发电路保持第二数据值恒定，使得它总是响应于图案的相同边缘来确定触发信号。在顺序操作模式中，触发电路在每次断言触发信号时改变第二数据的值，使得响应于数字信号模式的不同边缘发生触发信号的连续断言。

5. 发明授权

US07352204B2 Automatic skew correction for differential signals 有权
标题翻译：差分信号的自动偏差校正
公开(公告)号：US07352204B2
公开(公告)日：2008-04-01
申请号：US11413717
申请日：2006-04-28
申请人： Arnold M. Frisch
发明人： Arnold M. Frisch
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K5/156 , G01R31/31706 , G01R31/31725 , H03K5/151 , H04L25/0272 , H04L25/0292 , H04L25/085
摘要： A skew correction system incorporated into a transmitter forwarding a differential signal on a differential lane monitors returning signal reflections when the receiving end of the differential lane is appropriately terminated. Based on an analysis of the reflections, the skew correction system adjusts the relative timing of complementary edges of the differential signal departing the transmitter so as to substantially eliminate skew at the receiving end of the differential lane.
摘要翻译：在差分通道上转发差分信号的发送器中的偏斜校正系统监视差分通道的接收端适当地终止时的返回信号反射。基于对反射的分析，偏斜校正系统调整离开发射机的差分信号的互补边缘的相对定时，以便基本上消除差分通道接收端的偏移。

6. 发明授权

US5905383A Multi-chip module development substrate 失效
标题翻译：多芯片模块开发基板
公开(公告)号：US5905383A
公开(公告)日：1999-05-18
申请号：US521148
申请日：1995-08-29
申请人： Arnold M. Frisch
发明人： Arnold M. Frisch
IPC分类号： G01R31/317 , G01R31/28 , H01L21/66 , H01L21/82 , H01L21/822 , H01L23/12 , H01L27/04 , G01R31/26
CPC分类号： G01R31/2884
摘要： A multi-chip module development substrate (12) contains embedded test circuitry (30). Vias (38) connect I/O channels (Cn) of the test circuitry with conductive runs in interconnect layers (16,18) that are part of an interconnect structure (17) of the development substrate. Integrated circuit chips (14) are then mounted on the multi-chip module development substrate in selected electrical contact with the conductive runs. The embedded test circuitry includes multiple timing analyzer circuits (TAn) and multiple analog probe circuits en). In a preferred embodiment, these timing analyzer circuits and analog probe circuits are provided in redundant pairs, with a pair of each associated with each of the I/O channels. Multiple pairs of each kind of circuit are grouped within test cells (70) physically arranged in rectangular areas. Adjacent test circuit cells may be rotated with respect to each other to achieve more efficient connections to interconnect structure. After verification testing for proper operation of the multi-chip module circuitry, production versions of the multi-chip module are fabricated on multi-chip module production substrates not containing the test circuitry, thereby removing the extra cost and complexity associated with the development substrate.
摘要翻译：多芯片模块开发基板（12）包含嵌入式测试电路（30）。通孔（38）将测试电路的I / O通道（Cn）与作为显影衬底的互连结构（17）的一部分的互连层（16,18）中的导电运行连接。然后将集成电路芯片（14）安装在多芯片模块显影基板上，与导电电流选择电接触。嵌入式测试电路包括多个定时分析器电路（TAn）和多个模拟探针电路。在优选实施例中，这些定时分析器电路和模拟探针电路以冗余对提供，其中每对与I / O通道中的每一个相关联。多对电路分为物理地布置在矩形区域内的测试单元（70）内。相邻的测试电路单元可以相对于彼此旋转以实现对互连结构的更有效的连接。在对多芯片模块电路进行正确操作的验证测试之后，多芯片模块的生产版本被制造在不包含测试电路的多芯片模块制造基板上，从而消除与显影基板相关联的额外成本和复杂性。

7. 发明授权

US07409617B2 System for measuring characteristics of a digital signal 失效
标题翻译：用于测量数字信号特性的系统
公开(公告)号：US07409617B2
公开(公告)日：2008-08-05
申请号：US10954572
申请日：2004-09-30
申请人： Thomas Arthur Almy , Arnold M. Frisch
发明人： Thomas Arthur Almy , Arnold M. Frisch
IPC分类号： G01R31/3173 , G01R31/3183
CPC分类号： G01R31/3191 , G01R31/31932
摘要： An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator for generating a series of trigger signal edges in response to selected DUT output signal edges occurring during separate repetitions of the digital signal pattern. The trigger generator can be configured to generate each trigger signal edge in response to the same or a different edge of the digital signal pattern. The apparatus determines when a DUT output signal edge occurs by determining when the DUT output signal rises above or falls below adjustable reference voltages. The apparatus alternatively responds to each trigger signal edge by measuring a period between two different edges of the digital signal pattern and or by repetitively sampling the DUT output signal to determine its state.
摘要翻译：被测电子设备（DUT）通过产生传送重复数字信号模式的数字DUT输出信号来响应数字输入信号。用于测量DUT输出信号的各种特性的装置包括触发发生器，用于响应于在数字信号模式的分开的重复期间发生的选定的DUT输出信号边沿产生一系列触发信号边沿。触发发生器可以被配置为响应于数字信号模式的相同或不同的边缘而产生每个触发信号边沿。该设备通过确定DUT输出信号何时上升或低于可调参考电压来确定DUT输出信号边沿何时发生。该装置通过测量数字信号模式的两个不同边缘之间的周期，或者通过重复采样DUT输出信号来确定其状态，交替地响应于每个触发信号边缘。

8. 发明授权

US5418470A Analog multi-channel probe system 失效
标题翻译：模拟多通道探头系统
公开(公告)号：US5418470A
公开(公告)日：1995-05-23
申请号：US139651
申请日：1993-10-22
申请人： Thomas P. Dagostino , Arnold M. Frisch
发明人： Thomas P. Dagostino , Arnold M. Frisch
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/318572 , G01R31/2884 , G01R31/31712 , G01R31/31715
摘要： A programmable analog multi-channel probe system is embedded within a device under test for coupling test points to external measurement points of the device under test. Programmable input buffer amplifiers are coupled to the test points to couple the data at those points to their outputs when enabled. The data from the input buffer amplifiers are input to respective routers to provide a plurality of outputs. Each common output from the routers is coupled as an input to an output buffer amplifier that provides the data as an output when enabled. The data at the output of the output buffer amplifiers is converted to a differential signal for transmission to the external measurement point by differential input/output amplifiers that have a reference level, selected from a plurality of reference levels including an internal reference level, as an input for comparison with the data from the output buffer amplifiers. A termination circuit may be provided for each output to provide appropriate impedance interface with the measurement points.
摘要翻译：可编程模拟多通道探头系统嵌入在被测器件内，将测试点耦合到被测器件的外部测量点。可编程输入缓冲放大器耦合到测试点，以在启用时将这些点处的数据耦合到其输出。来自输入缓冲放大器的数据被输入到相应的路由器以提供多个输出。来自路由器的每个公共输出作为输入耦合到输出缓冲放大器，其在启用时提供数据作为输出。输出缓冲放大器的输出端的数据被转换为差分信号，以通过差分输入/输出放大器传输到外部测量点，差分输入/输出放大器具有从包括内部参考电平的多个参考电平中选择的参考电平，作为输入与来自输出缓冲放大器的数据进行比较。可以为每个输出提供终端电路，以向测量点提供适当的阻抗接口。

9. 发明授权

US5060310A Apparatus and method for reduction of intermodulation distortion in an optical fiber network 失效
标题翻译：用于减少光纤网络中的互调失真的装置和方法
公开(公告)号：US5060310A
公开(公告)日：1991-10-22
申请号：US392175
申请日：1989-08-10
申请人： Arnold M. Frisch , Thomas A. Almy
发明人： Arnold M. Frisch , Thomas A. Almy
IPC分类号： H01L33/00 , H01S5/06 , H04B1/62 , H04B10/02 , H04B10/155 , H04B10/18
CPC分类号： H04B1/62 , H04B10/502 , H04B10/5053 , H04B2210/075
摘要： A low distortion optic fiber network having a feedback system which injects pilot tones into a base band input signal directly modulating an LED, optically detects the output resulting from the pilot tones, digitally samples the detected signal, and generates correction coefficients. The correction coefficients and the base band input signal are input to a correction circuit that pre-distorts the input signal in a non-linear manner and uses the distorted signal to modulate the LED. Pre-distorting the LED input signal compensates for the non-linearities of diode transfer characteristics and intermodulation between signals in the network thereby reducing harmonic and intermodulation distortion.

10. 发明授权

US4833350A Bipolar-CMOS digital interface circuit 失效
标题翻译：双极CMOS数字接口电路
公开(公告)号：US4833350A
公开(公告)日：1989-05-23
申请号：US187774
申请日：1988-04-29
申请人： Arnold M. Frisch
发明人： Arnold M. Frisch
IPC分类号： H03K5/02 , H03K19/0175 , H03K19/0185 , H03K19/0944
CPC分类号： H03K19/018521 , H03K19/09448
摘要： A bipolar-CMOS (Bi-CMOS) digital interface circuit (50) of the present invention provides an interface between a bipolar digital circuit (52) and a CMOS digital circuit (54). The digital interface circuit includes a digital transform circuit (56) that receives a bipolar logic signal generated by the bipolar digital circuit and transforms the signal into an intermediate logic signal whose voltage waveform is positioned symmetrically about a logic threshold generated by a CMOS digital input circuit (58). The CMOS digital input circuit receives the intermediate logic signal and generates a CMOS logic signal that is delivered to the CMOS digital circuit, thereby to interface the CMOS digital circuit with the bipolar digital circuit.

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