专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20210351342A1 SPIN-ORBIT TORQUE MRAM STRUCTURE AND MANUFACTURE THEREOF 有权
公开(公告)号：US20210351342A1
公开(公告)日：2021-11-11
申请号：US16871779
申请日：2020-05-11
申请人： Applied Materials, Inc.
发明人： Minrui YUI , Wenhui WANG , Jaesoo AHN , Jong Mun KIM , Sahil PATEL , Lin XUE , Chando PARK , Mahendra PAKALA , Chentsau Chris YING , Huixiong DAI , Christopher S. Ngai
IPC分类号： H01L43/08 , H01L43/04 , H01L43/14 , H01L43/10 , G11C11/16 , H01L27/22 , G01R33/09
摘要： Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

2. 发明公开

US20230389441A1 SPIN-ORBIT TORQUE MRAM STRUCTURE AND MANUFACTURE THEREOF 审中-公开
公开(公告)号：US20230389441A1
公开(公告)日：2023-11-30
申请号：US18231414
申请日：2023-08-08
申请人： Applied Materials, Inc.
发明人： Minrui YU , Wenhui WANG , Jaesoo AHN , Jong Mun KIM , Sahil PATEL , Lin XUE , Chando PARK , Mahendra PAKALA , Chentsau Chris YING , Huixiong DAI , Christopher S. NGAI
IPC分类号： H10N50/10 , G01R33/09 , G11C11/16 , H10B61/00 , H10N50/85 , H10N52/01 , H10N52/80
CPC分类号： H10N50/10 , G01R33/098 , G11C11/161 , G01R33/095 , H10B61/00 , H10N50/85 , H10N52/01 , H10N52/80
摘要： Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

3. 发明申请

US20150041061A1 RECURSIVE PUMPING FOR SYMMETRICAL GAS EXHAUST TO CONTROL CRITICAL DIMENSION UNIFORMITY IN PLASMA REACTORS 有权
标题翻译：用于对称气体排放以控制等离子体反应器中关键尺寸均匀性的循环泵
公开(公告)号：US20150041061A1
公开(公告)日：2015-02-12
申请号：US14452228
申请日：2014-08-05
申请人： Applied Materials, Inc.
发明人： Sergio Fukuda SHOJI , Hamid NOORBAKHSH , Jong Mun KIM , Jason Della ROSA , Ajit BALAKRISHNA
IPC分类号： C23C16/455 , H01L21/67 , F15D1/02 , H01J37/32
CPC分类号： C23C16/45591 , C23C16/4412 , F15D1/025 , H01J37/32633 , H01J37/32834
摘要： Embodiments of the present invention provide apparatus and methods for reducing non-uniformity and/or skews during substrate processing. One embodiment of the present invention provides a flow equalizer assembly for disposing between a vacuum port and a processing volume in a processing chamber. The flow equalizing assembly includes a first plate having at least one first opening, and a second plate having two or more second openings. The first and second plates define a flow redistributing volume therebetween, and the at least one first opening and the two or more second openings are staggered.
摘要翻译：本发明的实施例提供了用于在衬底处理期间减少不均匀性和/或偏斜的装置和方法。本发明的一个实施例提供了一种流量均衡器组件，用于在处理室中的真空口和处理容积之间设置。流量均衡组件包括具有至少一个第一开口的第一板和具有两个或更多个第二开口的第二板。第一和第二板限定其间的流动再分布体积，并且至少一个第一开口和两个或更多个第二开口交错。

4. 发明申请

US20150072530A1 METHODS FOR ETCHING MATERIALS USING SYNCHRONIZED RF PULSES 有权
标题翻译：使用同步RF脉冲蚀刻材料的方法
公开(公告)号：US20150072530A1
公开(公告)日：2015-03-12
申请号：US14020773
申请日：2013-09-06
申请人： Applied Materials, Inc.
发明人： Jong Mun KIM , Daisuke SHIMIZU , Katsumasa KAWASAKI , Sergio Fukuda SHOJI
IPC分类号： H01L21/3065 , H01L21/311
CPC分类号： H01L21/3065 , H01J37/32091 , H01J2237/334 , H01L21/31116
摘要： Embodiments of the present invention provide methods for etching a material layer using synchronized RF pulses. In one embodiment, a method includes providing a gas mixture into a processing chamber, applying a first RF source power at a first time point to the processing chamber to form a plasma in the gas mixture, applying a first RF bias power at a second time point to the processing chamber to perform an etching process on the substrate, turning off the first RF bias power at a third time point while continuously maintaining the first RF source power on from the first time point through the second and the third time points, and turning off the first RF source power at a fourth time point while continuously providing the gas mixture to the processing chamber from the first time point through the second, third and fourth time points.
摘要翻译：本发明的实施例提供了使用同步RF脉冲来蚀刻材料层的方法。在一个实施例中，一种方法包括将气体混合物提供到处理室中，在第一时间点将第一RF源功率施加到处理室以在气体混合物中形成等离子体，在第二时间施加第一RF偏置功率指向处理室，以对基板执行蚀刻处理，在第三时间点关闭第一RF偏置功率，同时从第一时间点到第二时间点和第三时间点持续保持第一RF源功率接通，以及在第四时间点关闭第一RF源功率，同时从第一时间点到第二，第三和第四时间点连续地将气体混合物提供到处理室。

5. 发明申请

US20150001180A1 PROCESS KIT FOR EDGE CRITICAL DIMENSION UNIFORMITY CONTROL 审中-公开
标题翻译：边缘关键尺寸均匀控制的工艺套件
公开(公告)号：US20150001180A1
公开(公告)日：2015-01-01
申请号：US14020774
申请日：2013-09-06
申请人： Applied Materials, Inc.
发明人： Kenny Linh DOAN , Jason Della ROSA , Hamid NOORBAKHSH , Jong Mun KIM
IPC分类号： H01J37/32 , B32B18/00
CPC分类号： H01J37/32642 , H01J37/32449 , H01J37/32623 , H01J37/32651
摘要： A tunable ring assembly, a plasma processing chamber having a tunable ring assembly and method for tuning a plasma process is provided. In one embodiment, a tunable ring assembly includes an outer ceramic ring having an exposed top surface and a bottom surface and an inner silicon ring configured to mate with the outer ceramic ring to define an overlap region, the inner silicon ring having an inner surface, a top surface and a notch formed between the inner surface and the top surface, the inner surface defining an inner diameter of the ring assembly, the notch is sized to accept an edge of a substrate, an outer portion of the top surface of the inner silicon ring configured to contact in the overlap region and underlying an inner portion of the bottom surface of the outer ceramic ring.
摘要翻译：提供了一种可调环组件，具有可调环组件的等离子体处理室和用于调谐等离子体工艺的方法。在一个实施例中，可调谐环组件包括具有暴露的顶表面和底表面的外陶瓷环和被配置为与外陶瓷环配合以限定重叠区域的内硅环，内硅环具有内表面，在所述内表面和所述顶表面之间形成的顶表面和凹口，所述内表面限定所述环组件的内径，所述凹口的尺寸设置成接受基底的边缘，所述内表面的顶表面的外部硅环构造成在重叠区域中接触并且位于外陶瓷环的底表面的内部下方。

6. 发明申请

US20190393024A1 RESIDUAL REMOVAL 审中-公开
公开(公告)号：US20190393024A1
公开(公告)日：2019-12-26
申请号：US16401883
申请日：2019-05-02
申请人： Applied Materials, Inc.
发明人： Jong Mun KIM , Biao LIU , Cheng PAN , Erica CHEN , Chentsau YING , Srinivas NEMANI , Ellie YIEH
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/311
摘要： Methods for removing residuals after a selective deposition process are provided. In one embodiment, the method includes performing a selective deposition process to form a metal containing dielectric material at a first location of a substrate and performing a residual removal process to remove residuals from a second location of the substrate.

7. 发明申请

US20180142354A1 RECURSIVE PUMPING FOR SYMMETRICAL GAS EXHAUST TO CONTROL CRITICAL DIMENSION UNIFORMITY IN PLASMA REACTORS 审中-公开
公开(公告)号：US20180142354A1
公开(公告)日：2018-05-24
申请号：US15875726
申请日：2018-01-19
申请人： Applied Materials, Inc.
发明人： Sergio Fukuda SHOJI , Hamid NOORBAKHSH , Jong Mun KIM , Jason DELLA ROSA , Ajit BALAKRISHNA
IPC分类号： C23C16/455 , C23C16/44 , H01J37/32 , F15D1/02
CPC分类号： C23C16/45591 , C23C16/4412 , F15D1/025 , H01J37/32633 , H01J37/32834
摘要： Embodiments of the present invention provide apparatus and methods for reducing non-uniformity and/or skews during substrate processing. One embodiment of the present invention provides a flow equalizer assembly for disposing between a vacuum port and a processing volume in a processing chamber. The flow equalizing assembly includes a first plate having at least one first opening, and a second plate having two or more second openings. The first and second plates define a flow redistributing volume therebetween, and the at least one first opening and the two or more second openings are staggered.

8. 发明公开

US20240249936A1 METHODS FOR REDUCING MICRO AND MACRO SCALLOPING ON SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20240249936A1
公开(公告)日：2024-07-25
申请号：US18158916
申请日：2023-01-24
申请人： Applied Materials, Inc.
发明人： Mang-Mang LING , Jong Mun KIM , Srinivas D. NEMANI , Ellie Y. YIEH
IPC分类号： H01L21/02 , H01L21/033 , H01L21/3213 , H01L21/768
CPC分类号： H01L21/02244 , H01L21/02238 , H01L21/0332 , H01L21/0337 , H01L21/32137 , H01L21/32139 , H01L21/76816
摘要： Embodiments of the present disclosure relate to methods for patterning a material layer on a substrate. The method includes forming a hard mask layer on a material layer disposed on a substrate. The material layer includes a plurality of first layers and a plurality of second layers alternately formed over the substrate. The method further includes performing a first etch process to form features in the material layer through the hard mask layer by supplying a first etching gas; performing an oxidation process to oxidize a sidewall of the features by supplying an oxidation gas; and performing a second etch process to etch the sidewall of the features formed in the material layer by suppling a second etching gas.

9. 发明申请

US20210143323A1 Methods for etching a structure for MRAM Applications 有权
公开(公告)号：US20210143323A1
公开(公告)日：2021-05-13
申请号：US16681351
申请日：2019-11-12
申请人： Applied Materials, Inc.
发明人： Jong Mun KIM , Minrui YU , Chando PARK , Mang-Mang LING , Jaesoo AHN , Chentsau Chris YING , Srinivas D. NEMANI , Mahendra PAKALA , Ellie Y. YIEH
IPC分类号： H01L43/12 , H01L27/22 , H01L43/02 , H01L43/10
摘要： Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.

10. 发明申请

US20210017641A1 CARBON LAYER COVERED MASK IN 3D APPLICATIONS 有权
公开(公告)号：US20210017641A1
公开(公告)日：2021-01-21
申请号：US16904396
申请日：2020-06-17
申请人： Applied Materials, Inc.
发明人： Mang-Mang LING , Thomas KWON , Jong Mun KIM , Chentsau Chris YING
IPC分类号： C23C16/04 , C23C16/26 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： Embodiments of the present disclosure generally relate to a method for forming an opening using a mask. In one embodiment, a method includes forming a mask on a feature layer. The method includes forming a first opening in the mask to expose a portion of the feature layer. The method further includes forming a carbon layer on the mask and the exposed portion of the feature layer. The method also includes removing portions of the carbon layer and a portion of the exposed portion of the feature layer in order to form a second opening in the feature layer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式