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1. 发明授权

US07003066B1 Digital phase locked loop with phase selector having minimized number of phase interpolators 有权
标题翻译：具有相位选择器的数字锁相环具有最小数量的相位内插器
公开(公告)号：US07003066B1
公开(公告)日：2006-02-21
申请号：US10006559
申请日：2001-12-03
申请人： Antony Davies , Chienkuang Chen , Ling Wang
发明人： Antony Davies , Chienkuang Chen , Ling Wang
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/095 , H04L7/0337
摘要： In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.
摘要翻译：在本发明的一个实施例中，相位选择单元用于产生恢复的时钟信号（SCLK），相位选择信号发生器响应于来自数字滤波器的FWD信号和BWD信号产生相位选择信号。如果SDIN（串行数字输入）信号的相位导致恢复的时钟信号的相位，则数字滤波器置位FWD信号，并且如果SDIN（串行数字输入）信号的相位滞后于相位，则断言BWD信号恢复时钟信号。多路复用器接收以预定相位顺序排列的多个给定时钟信号，并输出所选择的第一和第二输出时钟信号，每一个是给定的时钟信号之一。相位插值器从多路复用器接收所选择的第一和第二输出时钟信号，以产生具有在第一和第二输出时钟信号的相位之间被相位插值的相位的恢复时钟信号。

2. 发明授权

US06993108B1 Digital phase locked loop with programmable digital filter 有权
标题翻译：带可编程数字滤波器的数字锁相环
公开(公告)号：US06993108B1
公开(公告)日：2006-01-31
申请号：US10006516
申请日：2001-12-03
申请人： Kuang Chi , Ling Wang , Antony Davies
发明人： Kuang Chi , Ling Wang , Antony Davies
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/089 , H03L7/093 , H04J3/0605 , H04L7/0025 , H04L7/0337
摘要： In a digital filter of a DPLL (digital phase locked loop) for minimizing the bit error rate for multiple communications protocols, a first reloadable register portion stores a TBW (total bandwidth) value programmed into the first reloadable register portion through a first port, and a second reloadable register portion stores a DBW (differential bandwidth) value programmed into the second reloadable register portion through a second port. An up—counter generates an UP—CNT value by counting up each UP signal pulse generated by a phase transition detector when a first phase of a SDIN (serial data input) signal leads a second phase of a current ACLK (recovered clock) signal. A down—counter generates a DOWN—CNT value by counting up each DOWN signal pulse generated by the phase transition detector when the first phase of the SDIN (serial data input) signal lags the second phase of the current ACLK (recovered clock) signal. One of a FWD (forward) signal or a BWD (backward) signal are asserted or are both not asserted depending on the UP—CNT value and the DN—CNT value in comparison to the TBW value and the DBW value. Another clock signal having a leading phase from the current ACLK signal is selected as a new ACLK (recovered clock) signal when the FWD signal is asserted. Or, another clock signal having a lagging phase from the current ACLK signal is selected as the new ACLK (recovered clock) signal when the BWD signal is asserted. Or, the current ACLK signal remains as the new ACLK (recovered clock) signal if neither the FWD signal nor the BWD signal is asserted.
摘要翻译：在用于最小化多个通信协议的误码率的DPLL（数字锁相环）的数字滤波器中，第一可重新加载的寄存器部分通过第一端口将经编程的TBW（总带宽）值存储到第一可重新加载的寄存器部分中，以及第二可重新加载的寄存器部分通过第二端口存储编程到第二可重新加载的寄存器部分中的DBW（差分带宽）值。通过在SDIN（串行数据输入）信号的第一相位上递增由相变检测器产生的每个UP信号脉冲，上计数器 - 计数器产生UP CNT值导致当前ACLK（恢复时钟）信号的第二阶段。计数器通过在SDIN（串行数据输入）信号的第一相位上递增由相变检测器产生的每个DOWN信号脉冲，产生一个DOWN 滞后于当前ACLK（恢复时钟）信号的第二阶段。 FWD（正向）信号或BWD（反向）信号中的一个被断言或者两者都不被断言，这取决于CNT的值和DN < - > CNT值与TBW值和DBW值进行比较。当FWD信号被断言时，具有来自当前ACLK信号的引导相位的另一时钟信号被选择为新的ACLK（恢复时钟）信号。或者，当BWD信号有效时，选择具有来自当前ACLK信号的滞后相位的另一时钟信号作为新的ACLK（恢复时钟）信号。或者，如果FWD信号和BWD信号都不被断言，则当前的ACLK信号保持为新的ACLK（恢复时钟）信号。

3. 发明申请

US20050222456A1 Synthesis of cyclohexanone derivatives 失效
标题翻译：环己酮衍生物的合成
公开(公告)号：US20050222456A1
公开(公告)日：2005-10-06
申请号：US10522261
申请日：2003-07-30
申请人： Karel Brands , Antony Davies , Paul Oakley , Jeremy Scott , Duncan Shaw , Martin Teall
发明人： Karel Brands , Antony Davies , Paul Oakley , Jeremy Scott , Duncan Shaw , Martin Teall
IPC分类号： C07C315/04 , C07C317/24 , C07C317/44
CPC分类号： C07C315/04 , C07C2601/14 , C07C317/24 , C07C317/44
摘要： A novel process for preparing cyclohexanones (1) is described. The products are useful as gamma-secretase in-hibitors, or as intermediates in the synthesis of other gamma-secretase inhibitors.
摘要翻译：描述了一种制备环己酮（1）的新方法。该产品可用作γ-分泌酶抑制剂，或作为合成其它γ-分泌酶抑制剂的中间体。

4. 发明申请

US20100197525A1 SUBSTANCE AND A DEVICE 有权
标题翻译：物质和设备
公开(公告)号：US20100197525A1
公开(公告)日：2010-08-05
申请号：US12450117
申请日：2008-03-13
申请人： Antony Davies , Siobhan Mitchell , Dermot Kelleher , Yuri Volkov
发明人： Antony Davies , Siobhan Mitchell , Dermot Kelleher , Yuri Volkov
IPC分类号： C40B60/00
CPC分类号： B01L3/50853 , B01L3/5085 , B01L2300/045 , B01L2300/049 , B01L2300/069 , B01L2300/0829 , B01L2300/1883 , C12M23/12
摘要： A device (1) for housing a scientific sample comprising at least one sample well (2) and an on-board buffering substance (3) wherein the onboard buffering substance (3) at least partly surrounds the sample well (2). The on-board buffering substance (3) may be in the form of a matrix, such as a gel-like matrix. The device (1) may further comprise an insulating means. Also described is a substance for use in culturing and/or assaying a sample whereby the substance provides atmospheric and thermal buffering. The invention further provides a lid for a single-well or multi-well sample plate, the lid being configured to facilitate delivery of a sample through the lid into a well, and for sealing the well. The lid comprises moveable portions (52, 53) that have at least one orifice (54, 57) formed through the moveable portions (52, 53) such that a conduit is formed by alignment of the orifices (54, 57) of both the lid portions (52, 53).
摘要翻译：一种用于容纳包含至少一个样品阱（2）和板上缓冲物质（3）的科学样品的装置（1），其中所述载板缓冲物质（3）至少部分地围绕所述样品井（2）。板载缓冲物质（3）可以是基质的形式，例如凝胶状基质。装置（1）还可以包括绝缘装置。还描述了用于培养和/或测定样品的物质，由此物质提供大气和热缓冲。本发明还提供了一种用于单井或多孔样品板的盖子，该盖子构造成便于将样品通过盖子输送到井中并用于密封井。所述盖包括可移动部分（52,53），所述可移动部分具有通过所述可移动部分（52,53）形成的至少一个孔（54,57），使得通过所述孔的所述孔（54,57）盖部分（52,53）。

5. 发明申请

US20070225520A1 Stereoselective Synthesis of a 4,4-Disubstituted Cyclohexanepropanoic Acid 有权
标题翻译：立体选择性合成4,4-二取代的环己丙酸
公开(公告)号：US20070225520A1
公开(公告)日：2007-09-27
申请号：US10589098
申请日：2005-02-16
申请人： Karel Brands , Sarah Brewer , Antony Davies , Ulf Dolling , Deborah Hammond , David Lieberman , Jeremy Scott
发明人： Karel Brands , Sarah Brewer , Antony Davies , Ulf Dolling , Deborah Hammond , David Lieberman , Jeremy Scott
IPC分类号： C07C51/353 , C07C315/02 , C07C317/44 , C07C319/14 , C07C59/56 , C07C53/23 , C07C319/16 , C07C323/61
CPC分类号： C07C57/62 , C07B2200/09 , C07C51/60 , C07C59/56 , C07C315/02 , C07C319/14 , C07C319/16 , C07C2601/14 , C07C2601/16 , C07C63/68 , C07C317/44 , C07C323/61
摘要： There is provided stereoselective route to a compound of formula I: wherein R represents H or an alkali metal, Ar1 represents 4-chlorophenyl and Ar2 represents 2,5-difluorophenyl.
摘要翻译：提供了式I化合物的立体选择性途径：其中R表示H或碱金属，Ar 1表示4-氯苯基，Ar 2表示2,5-二氟苯基。

6. 发明授权

US06463457B1 System and method for the establishment and the utilization of networked idle computational processing power 失效
标题翻译：用于建立和利用网络空闲计算处理能力的系统和方法
公开(公告)号：US06463457B1
公开(公告)日：2002-10-08
申请号：US09648986
申请日：2000-08-28
申请人： Steven L. Armentrout , James O'Connor , James Gannon , Brian Sletten , Sean Cier , Sarah Carlson , Antony Davies , Jonathan Davis , Greg DuPertuis , Scott McLoughlin
发明人： Steven L. Armentrout , James O'Connor , James Gannon , Brian Sletten , Sean Cier , Sarah Carlson , Antony Davies , Jonathan Davis , Greg DuPertuis , Scott McLoughlin
IPC分类号： G06F1300
CPC分类号： G06F9/5072
摘要： A distributed computing platform using the idle computational processing power of a plurality of provider computers is disclosed. At least one networked server collects tasks from client computers, schedules and distributes the tasks to networked provider computers, and collects and returns results to client computers. A client API forms tasks and collects results. A compute engine operates on the provider computers to communicate with the server and execute tasks using idle computational power.
摘要翻译：公开了一种使用多个供应商计算机的空闲计算处理能力的分布式计算平台。至少一个联网服务器从客户端计算机收集任务，计划并将任务分配给联网的提供商计算机，并收集并将结果返回到客户端计算机。客户端API形成任务并收集结果。计算引擎在提供者计算机上进行操作以与服务器进行通信，并使用空闲的计算能力执行任务。

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