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1. 发明授权

US07062159B1 Device for correcting a digital estimate of an electric signal 有权
标题翻译：用于校正电信号的数字估计的装置
公开(公告)号：US07062159B1
公开(公告)日：2006-06-13
申请号：US11005707
申请日：2004-12-07
申请人： Antonio Borrello , Stefano Saggini , Aldo Novelli , Ignazio Bellomo
发明人： Antonio Borrello , Stefano Saggini , Aldo Novelli , Ignazio Bellomo
IPC分类号： H02P7/06
CPC分类号： H02P8/12
摘要： A device for correcting a digital estimate of an electric signal is described. The device includes a comparator that generates a current proportional to the difference between an analog estimate signal, which derives from the digital estimate, and the electric signal. The device also includes a capacitor positioned to be charged by the current, a transistor that discharges the capacitor, and a comparator that compares the voltage at the terminal of the capacitor with a reference voltage. The device also includes a controller that drives the transistor in response to the output signal of the comparator and a logic device that generates a correction digital signal to be added to or subtracted from the digital estimate of the electric signal in correspondence of an ascending or descending waveform of the electric signal.
摘要翻译：描述用于校正电信号的数字估计的装置。该装置包括一个比较器，该比较器产生与从数字估计导出的模拟估计信号和电信号之间的差成比例的电流。该器件还包括一个定位为由电流充电的电容器，一个对电容器进行放电的晶体管，以及将电容器端子处的电压与参考电压进行比较的比较器。该装置还包括响应于比较器的输出信号驱动晶体管的控制器，以及逻辑器件，该逻辑器件产生校正数字信号，该校正数字信号将相应于上升或下降对电信号的数字估计加或减电信号的波形。

2. 发明申请

US20060119495A1 DEVICE TO EFFECTUATE A DIGITAL ESTIMATE OF A PERIODIC ELECTRIC SIGNAL, RELATED METHOD AND CONTROL SYSTEM FOR AN ELECTRIC MOTOR WHICH COMPRISES SAID DEVICE 有权
标题翻译：影响周期性电信号的数字估计的装置，包含所述装置的电动机的相关方法和控制系统
公开(公告)号：US20060119495A1
公开(公告)日：2006-06-08
申请号：US11006432
申请日：2004-12-07
申请人： Antonio Borrello , Stefano Saggini , Aldo Novelli , Ignazio Bellomo
发明人： Antonio Borrello , Stefano Saggini , Aldo Novelli , Ignazio Bellomo
IPC分类号： H03M1/66
CPC分类号： H03M1/48
摘要： A device for effectuating a digital estimate of a periodic electric signal is described. The device comprising a linear DAC having an output signal, a comparator that compares the output signal of the linear DAC with the periodic electric signal, and logic circuitry having in input the output signal of the comparator and a pulse clock signal. The logic circuitry provides a first digital signal in input to the linear DAC and a second digital signal representative of the estimate of the periodic electric signal.
摘要翻译：描述了用于实现周期性电信号的数字估计的装置。该装置包括具有输出信号的线性DAC，将线性DAC的输出信号与周期性电信号进行比较的比较器以及输入比较器的输出信号和脉冲时钟信号的逻辑电路。逻辑电路提供输入到线性DAC的第一数字信号和表示周期性电信号的估计的第二数字信号。

3. 发明授权

US07084790B2 Device to effectuate a digital estimate of a periodic electric signal, related method and control system for an electric motor which comprises said device 有权
标题翻译：用于实现包括所述装置的电动机的周期性电信号的数字估计，相关方法和控制系统的装置
公开(公告)号：US07084790B2
公开(公告)日：2006-08-01
申请号：US11006432
申请日：2004-12-07
申请人： Antonio Borrello , Stefano Saggini , Aldo Novelli , Ignazio Bellomo
发明人： Antonio Borrello , Stefano Saggini , Aldo Novelli , Ignazio Bellomo
IPC分类号： H03M1/48
CPC分类号： H03M1/48
摘要： A device for effectuating a digital estimate of a periodic electric signal is described. The device comprising a linear DAC having an output signal, a comparator that compares the output signal of the linear DAC with the periodic electric signal, and logic circuitry having in input the output signal of the comparator and a pulse clock signal. The logic circuitry provides a first digital signal in input to the linear DAC and a second digital signal representative of the estimate of the periodic electric signal.
摘要翻译：描述了用于实现周期性电信号的数字估计的装置。该装置包括具有输出信号的线性DAC，将线性DAC的输出信号与周期性电信号进行比较的比较器以及输入比较器的输出信号和脉冲时钟信号的逻辑电路。逻辑电路提供输入到线性DAC的第一数字信号和表示周期性电信号的估计的第二数字信号。

4. 发明申请

US20060120699A1 DEVICE FOR CORRECTING A DIGITAL ESTIMATE OF AN ELECTRIC SIGNAL 有权
标题翻译：用于校正电信号数字估计的装置
公开(公告)号：US20060120699A1
公开(公告)日：2006-06-08
申请号：US11005707
申请日：2004-12-07
申请人： Antonio Borrello , Stefano Saggini , Aldo Novelli , Ignazio Bellomo
发明人： Antonio Borrello , Stefano Saggini , Aldo Novelli , Ignazio Bellomo
IPC分类号： H02P5/06
CPC分类号： H02P8/12
摘要： A device for correcting a digital estimate of an electric signal is described. The device includes a comparator that generates a current proportional to the difference between an analog estimate signal, which derives from the digital estimate, and the electric signal. The device also includes a capacitor positioned to be charged by the current, a transistor that discharges the capacitor, and a comparator that compares the voltage at the terminal of the capacitor with a reference voltage. The device also includes a controller that drives the transistor in response to the output signal of the comparator and a logic device that generates a correction digital signal to be added to or subtracted from the digital estimate of the electric signal in correspondence of an ascending or descending waveform of the electric signal.
摘要翻译：描述用于校正电信号的数字估计的装置。该装置包括一个比较器，该比较器产生与从数字估计导出的模拟估计信号和电信号之间的差成比例的电流。该器件还包括一个定位为由电流充电的电容器，一个对电容器进行放电的晶体管，以及将电容器端子处的电压与参考电压进行比较的比较器。该装置还包括响应于比较器的输出信号驱动晶体管的控制器，以及逻辑器件，该逻辑器件产生校正数字信号，该校正数字信号将相应于上升或下降对电信号的数字估计加或减电信号的波形。

5. 发明授权

US06381185B2 Method and a circuit architecture for testing an integrated circuit comprising a programmable, non-volatile memory 有权
标题翻译：用于测试包括可编程的非易失性存储器的集成电路的方法和电路架构
公开(公告)号：US06381185B2
公开(公告)日：2002-04-30
申请号：US09782969
申请日：2001-02-14
申请人： Alessandro Camera , Paolo Sandri , Ignazio Bellomo , Albino Pidutti
发明人： Alessandro Camera , Paolo Sandri , Ignazio Bellomo , Albino Pidutti
IPC分类号： G11C700
CPC分类号： G11C29/50004 , G06F2201/81 , G11C16/04 , G11C29/50
摘要： A method for testing a programmable, nonvolatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The programmed memory cells are addressed in succession to identify a lowest of threshold voltage levels. The addressing for each memory location includes applying a selection voltage that is lower than the lowest threshold voltage level corresponding to a memory location currently being addressed. The bits are read from the programmed memory cells for the memory location currently being addressed. The reading is repeated while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell. The low threshold voltage level is compared in the memory location currently being addressed as determined in the reading with a stored value corresponding to the lowest of the low threshold voltages of the memory locations previously addressed.
摘要翻译：提供了一种用于测试包括存储器单元矩阵的可编程非易失性存储器的方法。多个存储单元被编程。编程的存储器单元被连续寻址以识别阈值电压电平的最低值。每个存储器位置的寻址包括施加低于对应于当前被寻址的存储器位置的最低阈值电压电平的选择电压。这些位从当前正在寻址的存储器位置的已编程存储单元读取。重复读取，同时逐渐改变提供给对应于当前正被寻址的存储器位置的字线的选择电压，直到检测到当前被寻址的存储器位置中的至少一个位已经从对应于将编程的存储器单元读取到对应于非编程存储器单元的读取的第二逻辑电平。在当前正在寻址的存储器位置中，在读取中确定的低阈值电压电平与对应于先前寻址的存储器位置的最低阈值电压的存储值进行比较。

6. 发明申请

US20100168873A1 STATE MACHINE 有权
标题翻译：状态机
公开(公告)号：US20100168873A1
公开(公告)日：2010-07-01
申请号：US12644961
申请日：2009-12-22
申请人： Ales LOIDL , Ignazio Bellomo , Luca Giussani , David Vincenzoni
发明人： Ales LOIDL , Ignazio Bellomo , Luca Giussani , David Vincenzoni
IPC分类号： G05B13/04 , G05B11/01 , H03K3/00
CPC分类号： G06F1/025
摘要： A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.
摘要翻译：一种用于产生根据机器的当前状态产生不同信号的信号的状态机。状态机被配置为根据内部定时器的功能改变状态，并且作为表示状态机外部的事件的信号的函数。

7. 发明授权

US08415978B2 State machine for generating a pulse width modulation (PWM) waveform 有权
标题翻译：用于产生脉宽调制（PWM）波形的状态机
公开(公告)号：US08415978B2
公开(公告)日：2013-04-09
申请号：US12644961
申请日：2009-12-22
申请人： Ales Loidl , Ignazio Bellomo , Luca Giussani , David Vincenzoni
发明人： Ales Loidl , Ignazio Bellomo , Luca Giussani , David Vincenzoni
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , H03K19/173 , H03K3/00
CPC分类号： G06F1/025
摘要： A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.
摘要翻译：一种用于产生根据机器的当前状态产生不同信号的信号的状态机。状态机被配置为根据内部定时器的功能改变状态，并且作为表示状态机外部的事件的信号的函数。

8. 发明授权

US06538479B2 Power switch driver circuit having cross-coupled buffer circuits 有权
标题翻译：电源开关驱动电路具有交叉耦合缓冲电路
公开(公告)号：US06538479B2
公开(公告)日：2003-03-25
申请号：US09942110
申请日：2001-08-28
申请人： Ignazio Bellomo , Giulio Corva , Francesco Villa
发明人： Ignazio Bellomo , Giulio Corva , Francesco Villa
IPC分类号： H03K300
CPC分类号： H03K17/04123 , H03K17/08142 , H03K17/6871
摘要： A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.
摘要翻译：驱动器电路驱动至少一个电源开关，该电路包括在公共输出节点处连接到所述开关的互补成对的功率晶体管的最后级。有利地，该电路包括连接在每个功率晶体管的上游的相应的上电缓冲器级和与每个功率晶体管相关联的上电检测器，与功率晶体管中的一个连接到缓冲级的检测器的晶体管中的互补晶体管，以防止功率晶体管同时导通。

9. 发明授权

US06396251B2 Constant-frequency control circuit for a switching voltage regulator of the hysteretic type 有权
标题翻译：用于迟滞型开关电压调节器的恒频控制电路
公开(公告)号：US06396251B2
公开(公告)日：2002-05-28
申请号：US09800759
申请日：2001-03-06
申请人： Giulio Corva , Alessandro Camera , Ignazio Bellomo
发明人： Giulio Corva , Alessandro Camera , Ignazio Bellomo
IPC分类号： G05F156
CPC分类号： H02M3/1563 , H02M3/158
摘要： The invention relates to a control circuit for a hysteretic switching voltage regulator, which comprises a logic circuit driving an output stage; a hysteresis comparator comparing the voltage value at the output of the regulator with a reference voltage; a current sensor for sensing, through a comparator, the current drain of a load connected to the output of the regulator. This control circuit further comprises a device for adjusting the hysteresis range of the hysteresis comparator, and a hysteresis frequency sensing and controlling logic portion connected to the output of the hysteresis comparator, the logic portion acting on the frequency adjusting device.
摘要翻译：本发明涉及一种用于迟滞开关电压调节器的控制电路，其包括驱动输出级的逻辑电路; 比较调节器输出端的电压值与参考电压的滞后比较器; 电流传感器，用于通过比较器感测连接到调节器的输出的负载的电流消耗。该控制电路还包括用于调节滞后比较器的滞后范围的装置，以及连接到滞后比较器的输出的滞后频率感测和控制逻辑部分，逻辑部分作用在频率调节装置上。

10. 发明授权

US06772379B1 Apparatus for verifying the data retention in non-volatile memories 有权
标题翻译：用于验证非易失性存储器中的数据保留的装置
公开(公告)号：US06772379B1
公开(公告)日：2004-08-03
申请号：US09710089
申请日：2000-11-10
申请人： Alessandro Camera , Ignazio Bellomo , Paolo Sandri
发明人： Alessandro Camera , Ignazio Bellomo , Paolo Sandri
IPC分类号： G11C2900
CPC分类号： G11C29/50016 , G11C16/04 , G11C29/50
摘要： An apparatus for verifying the data retention in a non-volatile memory is described which comprises at least one multiplexer and at least one shift register. The multiplexer and the at least one shift register are disposed so that the data of the non-volatile memory are in input to the multiplexer the output of which is in turn in input to the at least one shift register. The apparatus comprises a logical circuitry which by suitable commands controls the data transfer from said multiplexer to said at least one shift register, the data loading and the output data shifting in said at least one shift register.
摘要翻译：描述了一种用于验证非易失性存储器中的数据保持的装置，其包括至少一个多路复用器和至少一个移位寄存器。多路复用器和至少一个移位寄存器被布置成使得非易失性存储器的数据被输入到多路复用器，其输出又被输入到至少一个移位寄存器。该装置包括逻辑电路，其通过适当的命令控制从所述多路复用器到所述至少一个移位寄存器的数据传输，数据加载和输出数据在所述至少一个移位寄存器中移位。

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