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1. 发明授权

US06396251B2 Constant-frequency control circuit for a switching voltage regulator of the hysteretic type 有权
标题翻译：用于迟滞型开关电压调节器的恒频控制电路
公开(公告)号：US06396251B2
公开(公告)日：2002-05-28
申请号：US09800759
申请日：2001-03-06
申请人： Giulio Corva , Alessandro Camera , Ignazio Bellomo
发明人： Giulio Corva , Alessandro Camera , Ignazio Bellomo
IPC分类号： G05F156
CPC分类号： H02M3/1563 , H02M3/158
摘要： The invention relates to a control circuit for a hysteretic switching voltage regulator, which comprises a logic circuit driving an output stage; a hysteresis comparator comparing the voltage value at the output of the regulator with a reference voltage; a current sensor for sensing, through a comparator, the current drain of a load connected to the output of the regulator. This control circuit further comprises a device for adjusting the hysteresis range of the hysteresis comparator, and a hysteresis frequency sensing and controlling logic portion connected to the output of the hysteresis comparator, the logic portion acting on the frequency adjusting device.
摘要翻译：本发明涉及一种用于迟滞开关电压调节器的控制电路，其包括驱动输出级的逻辑电路; 比较调节器输出端的电压值与参考电压的滞后比较器; 电流传感器，用于通过比较器感测连接到调节器的输出的负载的电流消耗。该控制电路还包括用于调节滞后比较器的滞后范围的装置，以及连接到滞后比较器的输出的滞后频率感测和控制逻辑部分，逻辑部分作用在频率调节装置上。

2. 发明授权

US06538479B2 Power switch driver circuit having cross-coupled buffer circuits 有权
标题翻译：电源开关驱动电路具有交叉耦合缓冲电路
公开(公告)号：US06538479B2
公开(公告)日：2003-03-25
申请号：US09942110
申请日：2001-08-28
申请人： Ignazio Bellomo , Giulio Corva , Francesco Villa
发明人： Ignazio Bellomo , Giulio Corva , Francesco Villa
IPC分类号： H03K300
CPC分类号： H03K17/04123 , H03K17/08142 , H03K17/6871
摘要： A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.
摘要翻译：驱动器电路驱动至少一个电源开关，该电路包括在公共输出节点处连接到所述开关的互补成对的功率晶体管的最后级。有利地，该电路包括连接在每个功率晶体管的上游的相应的上电缓冲器级和与每个功率晶体管相关联的上电检测器，与功率晶体管中的一个连接到缓冲级的检测器的晶体管中的互补晶体管，以防止功率晶体管同时导通。

3. 发明授权

US06630854B2 Controlled voltage monostable circuit 有权
公开(公告)号：US06630854B2
公开(公告)日：2003-10-07
申请号：US10047305
申请日：2002-01-14
申请人： Giulio Corva , Ignazio Bellomo
发明人： Giulio Corva , Ignazio Bellomo
IPC分类号： H03K3033
CPC分类号： G05F1/466
摘要： The present invention relates a monostable circuit adapted to provide a delay having a length inversely proportional to an input signal, characterized by comprising generating means (21, 22) adapted to generate a signal proportionally to an input signal (Vin) and to a corrective factor (35), comparing means (23) adapted to compare the value of said signal with a prefixed value range (Imin, Imax) and correcting means (24) adapted to correct said corrective factor (35) in the case that the value of said signal is out of said prefixed value range (Imin, Imax).

4. 发明授权

US06828766B2 Voltage regulator 有权
标题翻译：电压调节器
公开(公告)号：US06828766B2
公开(公告)日：2004-12-07
申请号：US10449759
申请日：2003-05-30
申请人： Giulio Corva , Adalberto Mariani
发明人： Giulio Corva , Adalberto Mariani
IPC分类号： G05F140
CPC分类号： H02M3/156 , H02M3/1588 , H02M2001/0025 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： A circuit device generates a signal proportional to the current circulating in an inductor and a current comparator, which is disabled by a stand-by signal, and is input with a feedback signal and with a signal proportional to the current circulating in the inductor and generates a logic comparison signal. A control logic, input with a logic comparison signal and the stand-by signal, drives the switch or the switches of a power stage. A clamp, connected in parallel to a capacitive branch, makes the feedback signal greater than a certain minimum threshold, to make the current that is delivered to the load, when the regulator is not in the stand-by state, greater than a certain minimum current.
摘要翻译：电路装置产生与在电感器和电流比较器中循环的电流成比例的信号，其被待机信号禁用，并且用反馈信号输入，并且与在电感器中循环的电流成比例的信号，并产生逻辑比较信号。具有逻辑比较信号和待机信号的控制逻辑输入驱动功率级的开关或开关。与电容分支并联连接的钳位电路使得反馈信号大于某一最小阈值，以便当调节器不处于待机状态时，使得传递到负载的电流大于某一最小值当前。

5. 发明授权

US06924632B2 Frequency/signal converter and switching regulator having such a converter 有权
标题翻译：具有这种转换器的频率/信号转换器和开关调节器
公开(公告)号：US06924632B2
公开(公告)日：2005-08-02
申请号：US10612335
申请日：2003-07-02
申请人： Adalberto Mariani , Giulio Corva
发明人： Adalberto Mariani , Giulio Corva
IPC分类号： G01R23/09 , H02M3/156 , H03K9/06 , G05F1/40 , G05F1/56
CPC分类号： H02M3/156 , G01R23/09 , H03K9/06
摘要： A frequency/signal converter is provided that receives an input clock signal and generates an output signal. The converter includes a first circuit that receives the input clock signal and generates first and second logic signals that are complementary with one another, a loop circuit that includes a first circuit line and a second circuit line that are each coupled between a first supply voltage and a second supply voltage, and an integrator device. A current proportional to the output signal of the converter flows in the loop circuit. The first and second circuit lines include first and second capacitive elements and first and second switches for interrupting current flow into the first and second capacitive elements, respectively. The first and second switches are controlled by the first and second logic signals, respectively. The first and second circuit lines are alternatively coupled to an input terminal of the integrator device in order to obtain a substantially constant voltage signal at the input terminal of the integrator device, and the integrator device provides the output signal of the converter. Also provided is a switching regulator for providing a regulated voltage to a load.
摘要翻译：提供了一种接收输入时钟信号并产生输出信号的频率/信号转换器。转换器包括第一电路，其接收输入时钟信号并产生彼此互补的第一和第二逻辑信号;环路电路，包括第一电路线和第二电路线，每个耦合在第一电源电压和第二电源电压和积分器装置。与转换器的输出信号成比例的电流在回路中流动。第一和第二电路线包括第一和第二电容元件以及分别用于中断流入第一和第二电容元件的电流的第一和第二开关。第一和第二开关分别由第一和第二逻辑信号控制。第一和第二电路线交替地耦合到积分器装置的输入端，以便在积分器装置的输入端获得基本恒定的电压信号，积分器装置提供转换器的输出信号。还提供了一种用于向负载提供调节电压的开关调节器。

6. 发明授权

US06897642B2 Multiphase buck type voltage regulator 有权
标题翻译：多相降压型稳压器
公开(公告)号：US06897642B2
公开(公告)日：2005-05-24
申请号：US10620310
申请日：2003-07-14
申请人： Adalberto Mariani , Giulio Corva
发明人： Adalberto Mariani , Giulio Corva
IPC分类号： H02M3/158 , G05F1/40
CPC分类号： H02M3/1584
摘要： A multiphase buck type voltage regulator having at least two phases and including a first switching means that selectively connect a supply voltage to a load through a first current path; a second switching means that selectively connect said supply voltage to said load through a second current path; a first activation circuit that activates said first switching means; a first delay circuit that deactivates said first switching means after a first period of time; a second activation circuit that activates said second switching means; a second delay circuit that after a second period of time deactivates said second switching means; said first period of time depends on said supply voltage and on the output voltage; said second period of time depends on said supply voltage and on a voltage proportional to the difference of current that flows in said first and second current path.
摘要翻译：一种具有至少两相的多相降压式电压调节器，包括：第一开关装置，其通过第一电流路径选择性地将电源电压连接到负载; 第二开关装置，其通过第二电流路径选择性地将所述电源电压连接到所述负载; 激活所述第一开关装置的第一激活电路; 第一延迟电路，其在第一时间段之后停用所述第一切换装置; 第二激活电路，其激活所述第二开关装置; 第二延迟电路，在第二时间段之后，使所述第二开关装置失效; 所述第一时间段取决于所述电源电压和输出电压; 所述第二时间段取决于所述电源电压和与在所述第一和第二电流路径中流动的电流差成比例的电压。

7. 发明授权

US06894471B2 Method of regulating the supply voltage of a load and related voltage regulator 有权
标题翻译：调节负载和相关电压调节器的电源电压的方法
公开(公告)号：US06894471B2
公开(公告)日：2005-05-17
申请号：US10449821
申请日：2003-05-30
申请人： Giulio Corva , Adalberto Mariani
发明人： Giulio Corva , Adalberto Mariani
IPC分类号： H02M3/156 , G05F1/40
CPC分类号： H02M3/156
摘要： The method is for regulating the supply voltage of a load via a switching voltage regulator having an inductor driven by at least a power switch for delivering current to an output capacitor having a certain parasitic series resistance, connected between the output node of the regulator and ground and to an electric load eventually connected in parallel to the output capacitor. The method includes establishing a reference voltage, generating a comparison signal as the sum of a first voltage signal proportional to the current circulating in the inductor and of a second voltage signal depending on the difference between the output voltage and the reference voltage and on the first voltage signal. The comparison signal is compared with at least a threshold for generating a logic signal that switches between an active state and an inactive state and viceversa each time that the threshold is crossed, and the turn on or the turn off of the switch is controlled as a function of the state of the logic signal.
摘要翻译：该方法是用于通过开关电压调节器来调节负载的电源电压，该开关电压调节器具有由至少一个电源开关驱动的电感器，用于将电流传递到具有一定寄生串联电阻的输出电容器，该输出电容器连接在调节器的输出节点和地以及最终并联连接到输出电容器的电负载。该方法包括建立参考电压，产生比较信号作为与电感器中循环的电流成比例的第一电压信号与根据输出电压和参考电压之间的差异的第二电压信号的和的总和，以及在第一电压信号。将比较信号与用于生成在活动状态和非活动状态之间切换的逻辑信号的阈值进行比较，并且每当阈值越过时反向，并且开关的导通或关闭被控制为功能状态的逻辑信号。

8. 发明授权

US06727742B2 High-voltage level shifting circuit with optimized response time 有权
标题翻译：高电压电平移位电路具有优化的响应时间
公开(公告)号：US06727742B2
公开(公告)日：2004-04-27
申请号：US10053638
申请日：2002-01-24
申请人： Adalberto Mariani , Giulio Corva
发明人： Adalberto Mariani , Giulio Corva
IPC分类号： H03L500
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A high-voltage level shifting circuit with optimized response time, comprising: an inverter having an input and an output, the inverter being connected between a first voltage and a second voltage whose difference remains constant over time; a resistor, in which one terminal is connected to the first voltage and a second terminal is connected to the input of the inverter; a high-voltage transistor, which is connected between the second terminal of the resistor and a current source whose switching on and off determine the level shifting of a digital signal; and a clamp transistor, which is connected between the first voltage and a node that is common to the resistor and to the high-voltage transistor. The gate terminal of the clamp transistor is connected to the output of the inverter.
摘要翻译：一种具有优化的响应时间的高压电平移动电路，包括：具有输入和输出的反相器，所述反相器连接在第一电压和第二电压之间，所述第一电压和第二电压的差随时间保持恒定; 电阻器，其中一个端子连接到第一电压，第二端子连接到逆变器的输入端; 连接在电阻器的第二端子和导通和断开的电流源之间的高压晶体管确定数字信号的电平移位; 以及钳位晶体管，其连接在第一电压和与电阻器共用的节点和高压晶体管之间。钳位晶体管的栅极端子连接到逆变器的输出端。

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