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1. 发明申请

US20070158179A1 Method and apparatus for improving symmetry of a layer deposited on a semiconductor substrate 审中-公开
标题翻译：用于改善沉积在半导体衬底上的层的对称性的方法和装置
公开(公告)号：US20070158179A1
公开(公告)日：2007-07-12
申请号：US11330366
申请日：2006-01-11
申请人： Anthony Ciancio , Jeffrey Chan
发明人： Anthony Ciancio , Jeffrey Chan
IPC分类号： C23C14/32 , C23C14/00
CPC分类号： C23C14/3464 , C23C14/046 , H01J37/3408 , H01J37/3423 , H01J37/3455
摘要： A method for forming a layer on a semiconductor substrate is provided. A semiconductor substrate having a central axis may be positioned a first distance from a first target and a second distance from a second target. The second target may have at least first and second portions on opposing sides of the central axis of the semiconductor substrate. The first and second targets may be exposed to a processing gas. First and second biases may be respectively applied to the first and second targets such that ions in the processing gas bombard the first and second targets and deposition particles are ejected from the first and second targets onto the semiconductor substrate.
摘要翻译：提供了一种在半导体衬底上形成层的方法。具有中心轴线的半导体衬底可以定位成离开第一目标的第一距离和距第二目标的第二距离。第二靶可以在半导体衬底的中心轴的相对侧上具有至少第一和第二部分。第一和第二靶可能暴露于处理气体。第一和第二偏压可以分别施加到第一和第二靶，使得处理气体中的离子轰击第一和第二靶，并且沉积颗粒从第一和第二靶标喷射到半导体衬底上。

2. 发明申请

US20050062130A1 Semiconductor device and making thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：US20050062130A1
公开(公告)日：2005-03-24
申请号：US10668694
申请日：2003-09-23
申请人： Anthony Ciancio , Mark Griswold , Amudha Irudayam , Jennifer Morrison
发明人： Anthony Ciancio , Mark Griswold , Amudha Irudayam , Jennifer Morrison
IPC分类号： H01L20060101 , H01L21/02 , H01L21/8242 , H01L29/76 , H01L31/119
CPC分类号： H01L28/75 , H01L21/31645 , H01L23/5223 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： By forming a conductive smoothing layer over the bottom electrode and/or a capacitor dielectric, a MIM capacitor with improved reliability due to reduction of geometrically enhanced electric fields and electrode smoothing is formed. In one embodiment, layer including a refractory metal or a refractory metal-rich nitride, is formed over a first capping layer formed of a refractory nitride. In addition, a second refractory metal or a refractory metal-rich nitride layer may be formed on the capacitor dielectric. The smoothing layer could also be used in other semiconductor devices, such as transistors between a gate electrode and a gate dielectric.
摘要翻译：通过在底部电极和/或电容器电介质上形成导电平滑层，形成由于减小了几何增强的电场和电极平滑而具有可靠性提高的MIM电容器。在一个实施方案中，在由耐火氮化物形成的第一覆盖层上形成包括难熔金属或难熔金属富氮化物的层。此外，可以在电容器电介质上形成第二难熔金属或难熔金属富氮的氮化物层。平滑层也可以用于其它半导体器件，例如栅极电极和栅极电介质之间的晶体管。

3. 发明授权

US07078785B2 Semiconductor device and making thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：US07078785B2
公开(公告)日：2006-07-18
申请号：US10668694
申请日：2003-09-23
申请人： Anthony Ciancio , Mark D. Griswold , Amudha R. Irudayam , Jennifer H. Morrison
发明人： Anthony Ciancio , Mark D. Griswold , Amudha R. Irudayam , Jennifer H. Morrison
IPC分类号： H01L29/00 , H01L29/76 , H01L29/94
CPC分类号： H01L28/75 , H01L21/31645 , H01L23/5223 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： By forming a conductive smoothing layer over the bottom electrode and/or a capacitor dielectric, a MIM capacitor with improved reliability due to reduction of geometrically enhanced electric fields and electrode smoothing is formed. In one embodiment, layer including a refractory metal or a refractory metal-rich nitride, is formed over a first capping layer formed of a refractory nitride. In addition, a second refractory metal or a refractory metal-rich nitride layer may be formed on the capacitor dielectric. The smoothing layer could also be used in other semiconductor devices, such as transistors between a gate electrode and a gate dielectric.
摘要翻译：通过在底部电极和/或电容器电介质上形成导电平滑层，形成由于减小了几何增强的电场和电极平滑而具有可靠性提高的MIM电容器。在一个实施方案中，在由耐火氮化物形成的第一覆盖层上形成包括难熔金属或难熔金属富氮化物的层。此外，可以在电容器电介质上形成第二难熔金属或难熔金属富氮的氮化物层。平滑层也可以用于其它半导体器件，例如栅极电极和栅极电介质之间的晶体管。

4. 发明授权

US07833806B2 Structure and method for fabricating cladded conductive lines in magnetic memories 有权
标题翻译：在磁存储器中制造包覆导电线的结构和方法
公开(公告)号：US07833806B2
公开(公告)日：2010-11-16
申请号：US12363404
申请日：2009-01-30
申请人： Kenneth H. Smith , Nicholas D. Rizzo , Sanjeev Aggarwal , Anthony Ciancio , Brian R. Butcher , Kelly Wayne Kyler
发明人： Kenneth H. Smith , Nicholas D. Rizzo , Sanjeev Aggarwal , Anthony Ciancio , Brian R. Butcher , Kelly Wayne Kyler
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , G11C11/161 , G11C11/1659 , H01L23/53238 , H01L2924/0002 , Y10S438/978 , H01L2924/00
摘要： A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover. A bit line or digit line so formed may optionally be tapered at the ends (182, 184) to prevent magnetic reversal of the bit line magnetic moment that otherwise may occur due to external magnetic fields.
摘要翻译：一种形成磁电子器件的方法包括形成围绕磁头（112）的电介质材料（114），蚀刻电介质材料（114）以在磁头（112）上方限定开口（122），而不暴露磁头 112），所述开口（122）具有侧壁，在所述电介质材料（118）上沉积包覆材料的覆盖层（132），包括在所述侧壁上方，通过溅射工艺去除所述绝缘层所述开口（122）和所述电介质材料（124）在所述磁头（112）上方，并且在所述开口（122）内形成导电材料（146）以形成位线（154）。该过程减少了诸如位（112）的边缘突出的过程不规则性引起的错误，从而在其上形成的包层（132）中产生缺陷。如此形成的位线或数字线可以可选地在端部（182,184）处是锥形的，以防止由于外部磁场而可能发生的位线磁矩的磁性反转。

5. 发明授权

US06309966B1 Apparatus and method of a low pressure, two-step nucleation tungsten deposition 有权
标题翻译：低压两步成核钨沉积的装置和方法
公开(公告)号：US06309966B1
公开(公告)日：2001-10-30
申请号：US09639183
申请日：2000-08-15
申请人： Shrinivas Govindarajan , Anthony Ciancio
发明人： Shrinivas Govindarajan , Anthony Ciancio
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76877 , H01L2221/1089
摘要： An apparatus and method of tungsten via fill using a low pressure, 2-step nucleation tungsten deposition process. The tungsten via fill includes a silane soak, a nucleation film growth, and a bulk tungsten film deposition. The nucleation film growth is a low pressure, 2-step process including a controlled first nucleation film growth and a second nucleation film growth. A wafer fabricating system that includes a film depositing system and a control system is used. The film depositing system includes a reaction chamber with at least one silane-containing gas source, a tungsten-containing gas source, and a substrate heating source. The control system instructs the silane-containing gas source and the tungsten-containing gas source to flow with a significantly higher ratio of silane-containing gas (SiH4) to form a first silane-rich nucleation layer. The control system then instructs the gas sources to flow with a higher ratio of tungsten-containing gas, such as WF6, to form a second tungsten nucleation layer. The low pressure, 2-step process results with improved nucleation film step coverage.
摘要翻译：使用低压2步成核钨沉积工艺的钨通孔填充的装置和方法。钨通孔填充物包括硅烷浸泡，成核膜生长和体积钨膜沉积。成核膜生长是包括受控的第一成核膜生长和第二成核膜生长的低压，两步法。使用包括膜沉积系统和控制系统的晶片制造系统。膜沉积系统包括具有至少一个含硅烷的气体源，含钨气体源和基板加热源的反应室。控制系统指示含硅烷气体源和含钨气体源以显着更高比例的含硅烷气体（SiH 4）流动以形成第一硅烷富集成核层。控制系统然后指示气体源以较高比例的含钨气体（例如WF 6）流动以形成第二钨成核层。低压，2步工艺可以提高成核膜的阶梯覆盖率。

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