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1. 发明申请

US20050125711A1 Method and system for defect evaluation using quiescent power plane current (IDDQ) voltage linearity 失效
标题翻译：使用静态功率平面电流（IDDQ）电压线性度进行缺陷评估的方法和系统
公开(公告)号：US20050125711A1
公开(公告)日：2005-06-09
申请号：US10728172
申请日：2003-12-03
申请人： Anne Gattiker , Phillip Nigh
发明人： Anne Gattiker , Phillip Nigh
IPC分类号： G01R31/30 , G06F11/00
CPC分类号： G01R31/3008
摘要： A method and system for defect evaluation using IDDQ voltage linearity provides improved IDDQ testing for determining whether manufacturing defects in a VLSI device are likely to cause functional faults. IDDQ data is collected at multiple power plane voltages (VDDs) for a test vector at which a fault is activated. The IDDQ vs. VDD is then examined and a range of VDDs over which the characteristic IDDQs are non-linear with respect to VDD is determined. Peaks in the first derivative of the IDDQ vs. VDD curve indicate a particular VDD at which the onset of non-linearity in the IDDQ occurs. The VDD point below which the curve is non-linear indicates the relative resistance of a fault with respect to the driving point resistance of the node at which the fault is located. The relative resistance is directly determinative of additional circuit delay cause by the fault and/or whether the fault will cause a logic level transmission failure. Therefore, the range of VDDs for which the IDDQ curve is linear provides a pass/fail indication that can be used to reject devices in manufacturing test.
摘要翻译：使用IDDQ电压线性度进行缺陷评估的方法和系统提供改进的IDDQ测试，用于确定VLSI设备中的制造缺陷是否可能导致功能故障。 IDDQ数据在多个电源平面电压（VDD）下收集，用于启动故障的测试矢量。然后检查IDDQ与VDD，并确定特性IDDQ相对于VDD是非线性的VDD范围。 IDDQ与VDD曲线的一阶导数中的峰值表示IDDQ中发生非线性发生的特定VDD。曲线非线性以下的VDD点表示故障相对于故障位置的节点的驱动点电阻的相对电阻。相对电阻直接决定了故障引起的附加电路延迟和/或故障是否会导致逻辑电平传输故障。因此，IDDQ曲线为线性的VDD的范围提供了可用于在制造测试中拒绝器件的通过/失败指示。

2. 发明申请

US20060158222A1 Testing using independently controllable voltage islands 失效
标题翻译：使用独立可控电压岛测试
公开(公告)号：US20060158222A1
公开(公告)日：2006-07-20
申请号：US10545961
申请日：2003-02-20
申请人： Anne Gattiker , Phil Nigh , Leah Pastel , Steven Oakland , Jody VanHorn , Paul Zuchowski
发明人： Anne Gattiker , Phil Nigh , Leah Pastel , Steven Oakland , Jody VanHorn , Paul Zuchowski
IPC分类号： H03K19/0175
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318575 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test, wherein each island source voltage may be independently controlled (106, 108) during test.
摘要翻译：一种电压岛结构，其中每个电压岛的源电压可以在基于扫描的测试期间独立地接通/关断或调节。该架构包括多个电压岛（102,104），每个电压岛由相应的岛源电压（VDDI 1，VDDI 2）供电，以及耦合到电压岛的测试电路（116），并由全局源在测试期间总是导通的电压（Vg），其中每个岛源电压可以在测试期间被独立地控制（106,108）。

3. 发明授权

US07400162B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07400162B2
公开(公告)日：2008-07-15
申请号：US10539247
申请日：2003-02-20
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

4. 发明申请

US20050090996A1 Method and system for analyzing quiescent power plane current (IDDQ) test data in very-large scale integrated (VLSI) circuits 失效
公开(公告)号：US20050090996A1
公开(公告)日：2005-04-28
申请号：US10695554
申请日：2003-10-28
申请人： Anne Gattiker
发明人： Anne Gattiker
IPC分类号： G01R19/00 , G01R31/30
CPC分类号： G01R31/3008
摘要： A method and system for analyzing quiescent power plane current test data in a very large scale integrated (VLSI) circuit provides diagnostic information and improved IDDQ testing for analyzing and detecting manufacturing defects in a VLSI device. A set of IDDQ test values is collected over a set of test vectors for a group of devices. Values that are detected as corresponding to activated defects (e.g., shorts) are discarded from the data set and the data set is checked for correlation between the remaining ostensibly defect-free data values and devices (or alternatively vectors) that do not correlate are discarded from the data set. Then, a regression is generated for each vector from and IDDQ values for each vector and the IDDQ values at a selected reference vector (excepting the reference vector). Next, the IDDQ values at each vector for each device are normalized by estimating an expected IDDQ value for that vector and device from the regression for the vector and the device's measured reference vector IDDQ value. A cross-correlation check is performed to determine whether the set of measurements represents a good set of ostensibly defect-free measurements. New values that are detected as corresponding to an activated defect are discarded and previously discarded values are potentially reclaimed. The above regression, normalization and discard procedure is repeated until the set of non-defect activated vectors is stable and the IDDQ measurements can be categorized into discrete categories. The categorized IDDQ values may be used for identifying and potentially diagnosing defective devices and/or acceptability of devices can be determined from the normalized IDDQ values.

5. 发明授权

US07564256B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07564256B2
公开(公告)日：2009-07-21
申请号：US12119834
申请日：2008-05-13
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

6. 发明授权

US07486098B2 Integrated circuit testing method using well bias modification 失效
标题翻译：集成电路测试方法采用井偏置修正
公开(公告)号：US07486098B2
公开(公告)日：2009-02-03
申请号：US11876066
申请日：2007-10-22
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： A method for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.
摘要翻译：一种用于测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过修改测试过程中的良好偏差来提高IDDQ测试和诊断的分辨率。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开布线的IC，允许在测试期间对阱电位进行外部控制（40）。通常，该方法依赖于使用阱偏压来改变晶体管阈值电压。

7. 发明申请

US20080036486A1 INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION 失效
公开(公告)号：US20080036486A1
公开(公告)日：2008-02-14
申请号：US11876066
申请日：2007-10-22
申请人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
发明人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

8. 发明申请

US20060071653A1 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US20060071653A1
公开(公告)日：2006-04-06
申请号：US10539247
申请日：2003-02-20
申请人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
发明人： Anne Gattiker , David Grosch , Marc Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul Zuchowski
IPC分类号： G01R19/00
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

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