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1. 发明授权

US07759960B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07759960B2
公开(公告)日：2010-07-20
申请号：US12103906
申请日：2008-04-16
申请人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

2. 发明授权

US06504392B2 Actively controlled heat sink for convective burn-in oven 失效
标题翻译：主动控制的散热器，用于对流老化烤箱
公开(公告)号：US06504392B2
公开(公告)日：2003-01-07
申请号：US09277233
申请日：1999-03-26
申请人： John A. Fredeman , David L. Gardell , Marc D. Knox , Mark R. LaForce
发明人： John A. Fredeman , David L. Gardell , Marc D. Knox , Mark R. LaForce
IPC分类号： G01R3102
CPC分类号： G01R1/0458
摘要： A socket for testing or burning-in electronic components has a cover including a heat sink and a sensor. The heat sink and sensor are spring loaded so they make direct, temporary contact to an electronic component in the socket during burn-in. A heat transferring device is coupled to each heat sink. The heat transferring device uses input from the sensor to provide heat or cooling to each heat sink to individually control the temperature of each component. The heat transferring device can be an electric heater or a cooling device, such as a fan. Both can also be used. A plurality of these sockets are used in a forced air convective oven for burning-in a plurality of electronic components at one time. The oven provides oven heating and cooling for all components while the socket heater and sensor provide individual temperature control for each component.
摘要翻译：用于测试或燃烧电子部件的插座具有包括散热器和传感器的盖。散热器和传感器是弹簧加载的，因此它们在老化期间与插座中的电子部件直接临时接触。传热装置连接到每个散热器。传热装置使用来自传感器的输入来向每个散热器提供热量或冷却，以分别控制每个部件的温度。传热装置可以是电加热器或诸如风扇的冷却装置。两者也可以使用。多个这样的插座用于强制空气对流烘箱，用于一次燃烧多个电子部件。烤箱为所有组件提供烤箱加热和冷却，而插座加热器和传感器为每个组件提供单独的温度控制。

3. 发明授权

US07332927B2 Apparatus for temporary thermal coupling of an electronic device to a heat sink during test 失效
标题翻译：用于在测试期间将电子设备临时热耦合到散热器的装置
公开(公告)号：US07332927B2
公开(公告)日：2008-02-19
申请号：US11743899
申请日：2007-05-03
申请人： Paul J. Aube , Normand Cote , Roger G. Gamache, Jr. , David L. Gardell , Paul M. Gaschke , Marc D. Knox , Denis D. Turcotte
发明人： Paul J. Aube , Normand Cote , Roger G. Gamache, Jr. , David L. Gardell , Paul M. Gaschke , Marc D. Knox , Denis D. Turcotte
IPC分类号： G01R31/26
CPC分类号： G01R31/2875 , G01R31/2867 , G01R31/2868
摘要： A method, system and apparatus for testing an integrated circuit chip. The system including: means for forming a liquid polyalphaolefine layer on a bottom surface of the integrated circuit chip, a top surface of the integrated circuit chip having and a bottom surface not having signal and power pads; means for placing a surface of a heat sink into physical contact with the bottom surface of the polyalphaolefine layer; means for electrically coupling the integrated circuit chip to a tester; means for electrically testing the integrated circuit chip; means for electrically de-coupling the integrated circuit chip from the tester; means for removing the heat sink from contact with the polyalphaolefine layer, all or a portion of the polyalphaolefine layer remaining on the bottom surface of the integrated circuit chip; and means for removing the polyalphaolefine layer from the bottom surface of the integrated circuit chip.
摘要翻译：一种用于测试集成电路芯片的方法，系统和装置。该系统包括：用于在集成电路芯片的底表面上形成液体聚α-烯烃层的装置，集成电路芯片的顶表面和没有信号和功率垫的底表面; 用于将散热器的表面放置成与聚α-烯烃精细层的底表面物理接触的装置; 用于将集成电路芯片电耦合到测试器的装置; 用于电测试集成电路芯片的装置; 用于将集成电路芯片与测试器电耦合的装置; 用于去除所述散热器与所述聚α-烯烃精氢层接触的装置，所述或部分所述聚α-烯烃精矿层残留在所述集成电路芯片的底表面上; 以及用于从集成电路芯片的底表面去除聚α-烯烃精细层的装置。

4. 发明授权

US08854073B2 Methods and apparatus for margin testing integrated circuits using asynchronously timed varied supply voltage and test patterns 有权
标题翻译：使用异步定时变化的电源电压和测试模式的集成电路余量测试的方法和装置
公开(公告)号：US08854073B2
公开(公告)日：2014-10-07
申请号：US13236696
申请日：2011-09-20
申请人： David A. Grosch , Marc D. Knox , Erik A. Nelson , Brian C. Noble
发明人： David A. Grosch , Marc D. Knox , Erik A. Nelson , Brian C. Noble
IPC分类号： G01R31/02 , G01R31/3187 , G01R31/30
CPC分类号： G01R31/30 , G01R31/3004
摘要： Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.
摘要翻译：集成电路边缘检验方法和装置。该方法包括：选择时钟频率，工作温度范围和用于对集成电路进行裕度测试的电源电压电平，其中时钟频率，工作温度范围和电源电压电平中的一个或多个在正常操作条件之外的集成电路; 对集成电路施加与所选择的电源电压电平设定的异步时变电源电压; 以选定的时钟频率运行集成电路芯片，并将集成电路保持在所选择的温度范围内; 对集成电路施加连续测试图案; 并监控集成电路是否发生故障。

5. 发明授权

US07567090B2 Liquid recovery, collection method and apparatus in a non-recirculating test and burn-in application 失效
标题翻译：非循环测试和老化应用中的液体回收，收集方法和设备
公开(公告)号：US07567090B2
公开(公告)日：2009-07-28
申请号：US11551735
申请日：2006-10-23
申请人： Normand Cote , Peter J. Demko , David L. Gardell , Jeffrey D. Gelorme , Marc D. Knox , George J. Lawson , Kathryn C. Rivera
发明人： Normand Cote , Peter J. Demko , David L. Gardell , Jeffrey D. Gelorme , Marc D. Knox , George J. Lawson , Kathryn C. Rivera
IPC分类号： G01R31/02
CPC分类号： G01R31/2877
摘要： A heat sink for use in the burn-in of an I/C chip, which chip has a generally “flat” surface. The heat sink has a “flat” surface with micro-channels therein, positioned to open and close in and out of contact against the flat surface of an I/C chip being burned-in. At least one liquid opening communicates with said essentially flat surface on the heat sink to continuously apply liquid between the heat sink and the chip. A liquid inlet is provided to supply liquid to said at least one liquid opening. A recovery channel is positioned to recover liquid from between the heat sink and the chip, and an exhaust member is provided to carry liquid from said recovery channel to the exterior of the heat sink. The invention also includes a method of burning-in a chip.
摘要翻译：用于I / C芯片老化的散热器，该芯片具有通常“平坦”的表面。散热器具有在其中具有微通道的“平坦”表面，定位成打开和关闭与被烧入的I / C芯片的平坦表面的接触和接触。至少一个液体开口与散热器上的所述基本平坦的表面连通，以在散热器和芯片之间连续地施加液体。提供液体入口以将液体供应到所述至少一个液体开口。定位回收通道以从散热器和芯片之间回收液体，并且提供排气构件以将液体从所述回收通道运送到散热器的外部。本发明还包括一种烧入芯片的方法。

6. 发明授权

US07564256B2 Integrated circuit testing methods using well bias modification 失效
标题翻译：集成电路测试方法采用偏置修正
公开(公告)号：US07564256B2
公开(公告)日：2009-07-21
申请号：US12119834
申请日：2008-05-13
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

7. 发明授权

US07486098B2 Integrated circuit testing method using well bias modification 失效
标题翻译：集成电路测试方法采用井偏置修正
公开(公告)号：US07486098B2
公开(公告)日：2009-02-03
申请号：US11876066
申请日：2007-10-22
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： A method for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.
摘要翻译：一种用于测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过修改测试过程中的良好偏差来提高IDDQ测试和诊断的分辨率。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开布线的IC，允许在测试期间对阱电位进行外部控制（40）。通常，该方法依赖于使用阱偏压来改变晶体管阈值电压。

8. 发明授权

US06577146B2 Method of burning in an integrated circuit chip package 有权
公开(公告)号：US06577146B2
公开(公告)日：2003-06-10
申请号：US09681539
申请日：2001-04-25
申请人： Roger G. Gamache , David L. Gardell , Marc D. Knox
发明人： Roger G. Gamache , David L. Gardell , Marc D. Knox
IPC分类号： G01R3102
CPC分类号： G01R31/2874 , G01R31/2863 , G01R31/287
摘要： An improved method of burn-in of I/C chips is provided wherein, at the beginning of the burn-in process, the thermal resistance between the heatsink and the chip is measured at reduced power, the maximum allowable thermal resistance between the chip and heatsink interface is calculated and compared to the actual thermal resistance of the interface. If the actual thermal resistance measured at the interface between the heatsink and the chip package is greater than the maximum allowable calculated thermal resistance, then the corrective action is initiated in order to prevent damage to the I/C chip during burn-in or increase efficient use of the test sites.

9. 发明申请

US20130069678A1 EFFICIENT METHODS AND APPARATUS FOR MARGIN TESTING INTEGRATED CIRCUITS 有权
标题翻译：有效的方法和装置测试集成电路
公开(公告)号：US20130069678A1
公开(公告)日：2013-03-21
申请号：US13236696
申请日：2011-09-20
申请人： David Grosch , Marc D. Knox , Erik A. Nelson , Brian C. Noble
发明人： David Grosch , Marc D. Knox , Erik A. Nelson , Brian C. Noble
IPC分类号： G01R31/30
CPC分类号： G01R31/30 , G01R31/3004
摘要： Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.
摘要翻译：集成电路边缘检验方法和装置。该方法包括选择时钟频率，工作温度范围和用于对集成电路进行裕度测试的电源电压电平，其中时钟频率，工作温度范围和电源电压电平中的一个或多个在正常操作条件之外的集成电路; 对集成电路施加与所选择的电源电压电平设定的异步时变电源电压; 以选定的时钟频率运行集成电路芯片，并将集成电路保持在所选择的温度范围内; 对集成电路施加连续测试图案; 并监控集成电路是否发生故障。

10. 发明申请

US20080211530A1 INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION 失效
标题翻译：集成电路测试方法使用良好的偏差修正
公开(公告)号：US20080211530A1
公开(公告)日：2008-09-04
申请号：US12103906
申请日：2008-04-16
申请人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne E. Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/2856 , G01R31/3004 , G01R31/3008
摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.
摘要翻译：测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。此外，这些方法在应力测试期间提供更有效的应力。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

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