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1. 发明授权

US07705439B2 Destructor integrated circuit chip, interposer electronic device and methods 有权
标题翻译：析晶器集成电路芯片，插件电子器件及方法
公开(公告)号：US07705439B2
公开(公告)日：2010-04-27
申请号：US11043626
申请日：2005-01-25
申请人： Cuong V. Pham , David E. Chubin , Aaron D. Kuan , Colleen L. Khalifa
发明人： Cuong V. Pham , David E. Chubin , Aaron D. Kuan , Colleen L. Khalifa
IPC分类号： H01L23/02
CPC分类号： H01L23/57 , H01L23/3128 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15192 , Y10S257/922 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip includes a first integrated circuit chip and a depression substrate attached to the integrated circuit chip, wherein the integrated circuit chip and the depression substrate define a cavity therebetween. The semiconductor chip also includes a stress sensitive material located in the cavity and a chemical located in the cavity, wherein detection of tampering causes a reaction by the chemical such that the semiconductor chip is at least partially destroyed.
摘要翻译：半导体芯片包括附接到集成电路芯片的第一集成电路芯片和凹陷基板，其中集成电路芯片和凹陷基板在其间限定空腔。半导体芯片还包括位于空腔中的应力敏感材料和位于空腔中的化学物质，其中篡改的检测导致化学品的反应，使得半导体芯片至少部分地被破坏。

2. 发明授权

US07880248B1 Destructor integrated circuit chip, interposer electronic device and methods 有权
标题翻译：析晶器集成电路芯片，插件电子器件及方法
公开(公告)号：US07880248B1
公开(公告)日：2011-02-01
申请号：US12368256
申请日：2009-02-09
申请人： Cuong V. Pham , David E. Chubin , Colleen L. Khalifa
发明人： Cuong V. Pham , David E. Chubin , Colleen L. Khalifa
IPC分类号： G01P15/08
CPC分类号： H01L23/573 , H01L23/576 , H01L2224/13 , H01L2224/16225 , H01L2224/48091 , H01L2224/48465 , H01L2924/10158 , Y10S257/922 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor device. The device includes a substrate and an integrated circuit chip. The device also includes an electrically or thermally reactive layer located between a top surface of the substrate and a bottom surface of the integrated circuit chip, wherein the reactive layer is positioned such that detection of tampering causes the reactive layer to be electrically or thermally energized such that the semiconductor device is at least partially destroyed.
摘要翻译：半导体器件。该器件包括衬底和集成电路芯片。该装置还包括位于基板的顶表面和集成电路芯片的底表面之间的电或热反应层，其中反应层被定位成使得检测篡改导致反应层被电或热激励，例如半导体器件至少部分被破坏。

3. 发明授权

US07489013B1 Destructor integrated circuit chip, interposer electronic device and methods 有权
标题翻译：析晶器集成电路芯片，插件电子器件及方法
公开(公告)号：US07489013B1
公开(公告)日：2009-02-10
申请号：US11252403
申请日：2005-10-17
申请人： David E. Chubin , Cuong V. Pham , Colleen L. Khalifa , Randall David Buller
发明人： David E. Chubin , Cuong V. Pham , Colleen L. Khalifa , Randall David Buller
IPC分类号： H01L23/06
CPC分类号： H01L23/573 , H01L23/576 , H01L2224/13 , H01L2224/48091 , H01L2224/48465 , H01L2224/73265 , H01L2924/10158 , Y10S257/922 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device. The device includes a substrate and an integrated circuit chip. The device also includes an electrically or thermally reactive layer located between a top surface of the substrate and a bottom surface of the integrated circuit chip, wherein the reactive layer is positioned such that detection of tampering causes the reactive layer to be electrically or thermally energized such that the semiconductor device is at least partially destroyed.
摘要翻译：半导体器件。该器件包括衬底和集成电路芯片。该装置还包括位于基板的顶表面和集成电路芯片的底表面之间的电或热反应层，其中反应层被定位成使得检测篡改导致反应层被电或热激励，例如半导体器件至少部分被破坏。

4. 发明授权

US08268668B1 Destructor integrated circuit chip, interposer electronic device and methods 有权
标题翻译：析晶器集成电路芯片，插件电子器件及方法
公开(公告)号：US08268668B1
公开(公告)日：2012-09-18
申请号：US12798733
申请日：2010-04-09
申请人： Cuong V. Pham , David E. Chubin , Aaron D. Kuan , Colleen L. Khalifa
发明人： Cuong V. Pham , David E. Chubin , Aaron D. Kuan , Colleen L. Khalifa
IPC分类号： H01L23/02
CPC分类号： H01L23/573 , H01L23/3128 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/09701 , H01L2924/15192 , H01L2924/00012 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of fabricating an electronic circuit including forming a first depression on a first surface of a first wafer and forming a second depression on the first surface of the first wafer. The second depression is adjacent the first depression and separated from the first depression by a wall. The method further includes locating an actuator on the wall and attaching a first surface of a second wafer to the first surface of the first wafer to cover the first and second depressions. A first portion of the second wafer and the first depression define a first reservoir to contain a first chemical, and a second portion of the second wafer and the second depression define a second reservoir to contain a second chemical.
摘要翻译：一种制造电子电路的方法，包括在第一晶片的第一表面上形成第一凹陷，并在第一晶片的第一表面上形成第二凹陷。第二凹陷与第一凹陷相邻，并与第一凹陷分隔开一个壁。该方法还包括将致动器定位在壁上并将第二晶片的第一表面附接到第一晶片的第一表面以覆盖第一和第二凹陷。第二晶片和第一凹陷的第一部分限定第一储存器以容纳第一化学品，第二晶片的第二部分和第二凹陷限定第二储存器以容纳第二化学品。

5. 发明申请

US20100032776A1 DESTRUCTOR INTEGRATED CIRCUIT CHIP, INTERPOSER ELECTRONIC DEVICE AND METHODS 有权
标题翻译：集成电路芯片，插电器电子设备及方法
公开(公告)号：US20100032776A1
公开(公告)日：2010-02-11
申请号：US11043626
申请日：2005-01-25
申请人： Cuong V. Pham , David E. Chubin , Aaron D. Kuan , Colleen L. Khalifa
发明人： Cuong V. Pham , David E. Chubin , Aaron D. Kuan , Colleen L. Khalifa
IPC分类号： H01L23/06
CPC分类号： H01L23/57 , H01L23/3128 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15192 , Y10S257/922 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip includes a first integrated circuit chip and a depression substrate attached to the integrated circuit chip, wherein the integrated circuit chip and the depression substrate define a cavity therebetween. The semiconductor chip also includes a stress sensitive material located in the cavity and a chemical located in the cavity, wherein detection of tampering causes a reaction by the chemical such that the semiconductor chip is at least partially destroyed.
摘要翻译：半导体芯片包括附接到集成电路芯片的第一集成电路芯片和凹陷基板，其中集成电路芯片和凹陷基板在其间限定空腔。半导体芯片还包括位于空腔中的应力敏感材料和位于空腔中的化学物质，其中篡改的检测导致化学品的反应，使得半导体芯片至少部分地被破坏。

6. 发明授权

US08399781B1 Anti-tamper mesh 有权
标题翻译：防篡改网
公开(公告)号：US08399781B1
公开(公告)日：2013-03-19
申请号：US13045348
申请日：2011-03-10
申请人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
发明人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
IPC分类号： H01L23/48
CPC分类号： H05K3/125 , H05K1/0275 , H05K1/0284 , H05K1/0289 , H05K3/4664 , H05K2201/0999 , H05K2201/10151 , H05K2203/0126 , H05K2203/013 , H05K2203/1554 , Y10T29/49147 , Y10T29/49155
摘要： An electronic device includes at least one terminal formed on the electronic device. The electronic device also includes at least one of a semiconductor device, an integrated circuit chip, and a computer. A seamless conductive mesh is formed on at least one surface of the electronic device. The conductive mesh is in electrical contact with the terminal. The terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit. The electronic device also may include a pattern having traces formed on at least two surfaces where each of the traces includes a continuous loop of conductive material is formed on at least two surfaces. The electronic device also may include a first plurality of conductive loops formed on the electronic device that are continuous and surround the electronic device in a first direction and a second plurality of conductive loops formed on the electronic device that are continuous and surround the electronic device in a second direction.
摘要翻译：电子设备包括形成在电子设备上的至少一个终端。电子设备还包括半导体器件，集成电路芯片和计算机中的至少一个。在电子设备的至少一个表面上形成无缝导电网。导电网与端子电接触。该端子促进导电网和电检测电路之间的导电。电子设备还可以包括具有形成在至少两个表面上的迹线的图案，其中每个迹线包括导电材料的连续环形成在至少两个表面上。电子设备还可以包括形成在电子设备上的第一多个导电环路，其在第一方向上是连续的并围绕电子设备，并且形成在电子设备上的第二多个导电环路，其连续并围绕电子设备第二个方向。

7. 发明授权

US07947911B1 Anti-tamper mesh 有权
标题翻译：防篡改网
公开(公告)号：US07947911B1
公开(公告)日：2011-05-24
申请号：US11944771
申请日：2007-11-26
申请人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
发明人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
IPC分类号： H05K7/02
CPC分类号： H05K3/125 , H05K1/0275 , H05K1/0284 , H05K1/0289 , H05K3/4664 , H05K2201/0999 , H05K2201/10151 , H05K2203/0126 , H05K2203/013 , H05K2203/1554 , Y10T29/49147 , Y10T29/49155
摘要： A method of forming an anti-tamper mesh on an electronic device. The method includes forming at least one terminal on the electronic device and forming a conductive mesh on at least one surface of the electronic device, wherein the conductive mesh is in electrical contact with the terminal, and wherein the terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit.
摘要翻译：一种在电子设备上形成防篡改网的方法。该方法包括在电子设备上形成至少一个端子并在电子器件的至少一个表面上形成导电网，其中导电网与端子电接触，并且其中端子有利于导电网之间的导电和电检测电路。

8. 发明授权

US07640658B1 Methods for forming an anti-tamper pattern 有权
标题翻译：用于形成防篡改图案的方法
公开(公告)号：US07640658B1
公开(公告)日：2010-01-05
申请号：US11252402
申请日：2005-10-18
申请人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
发明人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： H05K3/125 , H05K1/0275 , H05K1/0284 , H05K1/0289 , H05K3/4664 , H05K2201/0999 , H05K2201/10151 , H05K2203/0126 , H05K2203/013 , H05K2203/1554 , Y10T29/49147 , Y10T29/49155
摘要： A method of forming an anti-tamper mesh on an electronic device. The method includes forming at least one terminal on the electronic device and forming a conductive mesh on at least one surface of the electronic device, wherein the conductive mesh is in electrical contact with the terminal, and wherein the terminal facilitates electrical conduction between the conductive mesh and an electrical detection circuit.
摘要翻译：一种在电子设备上形成防篡改网的方法。该方法包括在电子设备上形成至少一个端子并在电子器件的至少一个表面上形成导电网，其中导电网与端子电接触，并且其中端子有利于导电网之间的导电和电检测电路。

9. 发明授权

US08240038B1 Method for forming an anti-tamper mesh 有权
标题翻译：形成防篡改网的方法
公开(公告)号：US08240038B1
公开(公告)日：2012-08-14
申请号：US12653919
申请日：2009-12-21
申请人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
发明人： Cuong V. Pham , David E. Chubin , Robert A. Clarke , Aaron D. Kuan
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： H05K3/125 , H05K1/0275 , H05K1/0284 , H05K1/0289 , H05K3/4664 , H05K2201/0999 , H05K2201/10151 , H05K2203/0126 , H05K2203/013 , H05K2203/1554 , Y10T29/49147 , Y10T29/49155
摘要： A method including positioning an electronic device proximate a second device, the electronic device including at least one of a semiconductor device, an integrated circuit chip, and an electronic substrate, and the second device activatable to form a conductive pattern on the electronic device. The method further includes activating the second device to form the conductive pattern and forming the conductive pattern on at least two surfaces of the electronic device. The conductive pattern includes one or more than one conductive trace. Each conductive trace includes a conductive material and is continuous between at least two surfaces of the electronic device. Each conductive trace is formed by controlling relative movement of the electronic device and the second device during activation of the second device.
摘要翻译：一种包括将电子设备定位在第二设备附近的方法，所述电子设备包括半导体器件，集成电路芯片和电子衬底中的至少一个，并且所述第二器件可激活以在所述电子器件上形成导电图案。该方法还包括激活第二装置以形成导电图案并在电子装置的至少两个表面上形成导电图案。导电图案包括一个或多个导电迹线。每个导电迹线包括导电材料并且在电子器件的至少两个表面之间是连续的。每个导电迹线通过在第二装置的激活期间控制电子装置和第二装置的相对运动来形成。

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