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    • 5. 发明授权
    • RFID transponder chip with a programmable wake-up
    • RFID应答器芯片具有可编程唤醒功能
    • US08702008B2
    • 2014-04-22
    • US13488765
    • 2012-06-05
    • James SpringerDavid A. Kamp
    • James SpringerDavid A. Kamp
    • G06K19/06
    • G06K19/0701G06K19/0723
    • An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.
    • RFID应答器芯片包括至少一个用于拾取和发送射频信号的天线,整流器,用于在拾取的射频信号的整流电压下在至少一个电容器上存储电荷,上电复位电路 如果整流的电压电平小于用于操作逻辑单元的上电复位电路的上电复位或唤醒电压,则将逻辑单元维持在复位状态。 RFID应答器芯片还包括非易失性存储器,其中存储一个或多个修整值。 所述非易失性存储器直接连接到上电复位电路,以能够提供至少一个修整值,以在低于唤醒电压电平的整流电压电平下修整上电复位电路。
    • 6. 发明授权
    • Self-powered event detection device
    • 自供电事件检测装置
    • US08422293B2
    • 2013-04-16
    • US12945138
    • 2010-11-12
    • David A. KampFilippo MarinelliThierry Roz
    • David A. KampFilippo MarinelliThierry Roz
    • G11C16/22
    • G08B13/06E05B39/00E05B45/06E05B51/023E05B67/22E05B2047/0058E05B2047/0062E05B2047/0064G08B29/181
    • The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.
    • 所述自供电检测装置包括非易失性存储单元和由物理或化学作用或现象激活的传感器,所述传感器形成能量收集器,其将能量从物理或化学作用或现象转换成电刺激脉冲,所述存储器单元 布置成通过使用电刺激脉冲的电力来存储与传感器相关的至少第一物理或化学作用或现象的至少一点信息。 非易失性存储单元包括具有控制栅极的FET晶体管,限定第一输入的第一扩散和限定第二输入的第二扩散。 当在检测模式中,它在设定端子上接收由第一物理或化学作用或现象产生的电压刺激信号时,该FET晶体管从其初始逻辑状态被设置为其写入逻辑状态。
    • 7. 发明授权
    • Apparatus and method for testing ferroelectric memories
    • 用于测试铁电存储器的装置和方法
    • US06658608B1
    • 2003-12-02
    • US09400210
    • 1999-09-21
    • David A. KampGary F. Derbenwick
    • David A. KampGary F. Derbenwick
    • G11C2900
    • G11C29/028G11C11/22G11C29/50
    • A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. A known logic state is written to the memory cells, the cells are heated, and then read to provide output data indicative of the likelihood of premature failure for each of the memory cells. Ferroelectric stress is applied to the cells either before or after the cells are written to by repeatedly applying a voltage to the cells corresponding to a logic state opposite that of the written logic state.
    • 铁电集成电路存储器件包括:多个存储单元,每个存储单元包括铁电材料,多个导线,每个导体线连接到或连接到选定的一个存储单元; 驱动电路,用于将预定电压预定时间施加到所选择的导线中,所述预定电压和时间是对所述存储单元执行写或读功能所需的正常电压和时间,从所述组中选择的功能 将逻辑状态写入所选存储单元,并读取所选存储单元; 以及模式控制电路,其响应于外部信号用于调整所述预定电压或所述预定时间以执行从由以下组成的组中选择的操作:所选择的存储器单元的部分读取和所选存储单元的部分写入; 并向存储单元施加铁电应力。 将已知的逻辑状态写入存储器单元,单元被加热,然后读取以提供指示每个存储器单元的过早故障的可能性的输出数据。 通过对与逻辑状态相反的逻辑状态相对应的单元反复施加电压,在单元被写入之前或之后对电池施加铁电应力。
    • 8. 发明授权
    • Ferroelectric memory with shunted isolated nodes
    • 铁电存储器,分流隔离节点
    • US06256220B1
    • 2001-07-03
    • US09508305
    • 2000-03-09
    • David A. Kamp
    • David A. Kamp
    • G11C1127
    • H01L27/11502G11C11/22
    • A ferroelectric memory includes memory cells comprising a transistor having a source/drain, a ferroelectric capacitor having a first electrode and a second electrode. A plate line is connected to each of the second electrodes. In each memory cell, the first electrode is connected to the source/drain of the transistor to create a node that is isolated when the transistor is off. A shunt system directly electrically connects the isolated nodes of a pair of memory cells at a predetermined time to essentially equalize the voltages on the nodes. The shunt may be a Schottky diode, a resistor, and a pair of back-to-back diodes, or a transistor. In the embodiment in which the shunt is a transistor, the shunt line connected to the shunt transistor gate is boosted, there is a shunt transistor connecting each isolated node in a portion of the memory to the adjacent isolated node, and every eight to thirty-two isolated nodes, another shunt transistor connects the chain of isolated nodes to the plate line.
    • 铁电存储器包括具有源极/漏极的晶体管,具有第一电极和第二电极的铁电电容器的存储单元。 板线连接到每个第二电极。 在每个存储单元中,第一电极连接到晶体管的源极/漏极,以产生当晶体管截止时被隔离的节点。 分流系统在预定时间内直接电连接一对存储器单元的隔离节点,以基本上均衡节点上的电压。 分路可以是肖特基二极管,电阻器和一对背对背二极管或晶体管。 在分流器是晶体管的实施例中,连接到并联晶体管栅极的并联线被升压,存在将存储器的一部分中的每个隔离节点连接到相邻的隔离节点的并联晶体管, 两个隔离节点,另一个分流晶体管将隔离节点链连接到板线。
    • 9. 发明申请
    • TRANSPONDER WITH A MODULATOR
    • 带调制器的TRANSPONDER
    • US20120299641A1
    • 2012-11-29
    • US13478485
    • 2012-05-23
    • Nicolas PillinDavid A. Kamp
    • Nicolas PillinDavid A. Kamp
    • H03K3/01
    • G06K19/0723H01L29/78
    • A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.
    • RFID应答器包括电子电路和天线,该电子电路集成在p型衬底中,并且包括由PMOS晶体管形成的调制器,该PMOS晶体管的漏极电连接到天线的焊盘和源,连接到地 的电子电路布置在设置在p型衬底中的n型阱中。 PMOS晶体管具有由驱动电路驱动的栅极,该驱动电路被布置为提供至少一个负电压,该负电压足够低以响应由该电子电路的逻辑单元提供的控制信号而导通该PMOS晶体管。
    • 10. 发明申请
    • Identifying Radiation-Induced Inversions
    • 识别辐射诱导反转
    • US20080235636A1
    • 2008-09-25
    • US11690607
    • 2007-03-23
    • David A. Kamp
    • David A. Kamp
    • G06F17/50
    • G06F17/5081
    • A semiconductor layout design analyzer alerts a user of areas in a semiconductor layout design that may be candidates for radiation induced inversion. The analyzer includes means for gathering information, means for identifying, and means for alerting the user. The means for gathering gathers, from the layout design, placement information for thick oxide, low-doped p-type single crystal silicon, and n-type silicon. The means for identifying identifies, in the layout design, thick oxide overlaying low-doped p-type single crystal silicon and abutting n-type silicon. The means for alerting the user alerts the user of the identified areas of thick oxide.
    • 半导体布局设计分析仪向用户提供半导体布局设计中可能是辐射诱导反演的候选者的区域。 分析器包括用于收集信息的装置,用于识别的手段和用于警告用户的装置。 用于收集聚集的手段,从布局设计,厚氧化物,低掺杂p型单晶硅和n型硅的放置信息。 用于识别的手段在布局设计中识别厚氧化物覆盖低掺杂p型单晶硅和邻接的n型硅。 提醒用户的手段向使用者发出了确认的厚氧化物区域。