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    • 1. 发明授权
    • Self-powered event detection device
    • 自供电事件检测装置
    • US08422293B2
    • 2013-04-16
    • US12945138
    • 2010-11-12
    • David A. KampFilippo MarinelliThierry Roz
    • David A. KampFilippo MarinelliThierry Roz
    • G11C16/22
    • G08B13/06E05B39/00E05B45/06E05B51/023E05B67/22E05B2047/0058E05B2047/0062E05B2047/0064G08B29/181
    • The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.
    • 所述自供电检测装置包括非易失性存储单元和由物理或化学作用或现象激活的传感器,所述传感器形成能量收集器,其将能量从物理或化学作用或现象转换成电刺激脉冲,所述存储器单元 布置成通过使用电刺激脉冲的电力来存储与传感器相关的至少第一物理或化学作用或现象的至少一点信息。 非易失性存储单元包括具有控制栅极的FET晶体管,限定第一输入的第一扩散和限定第二输入的第二扩散。 当在检测模式中,它在设定端子上接收由第一物理或化学作用或现象产生的电压刺激信号时,该FET晶体管从其初始逻辑状态被设置为其写入逻辑状态。
    • 2. 发明授权
    • Self-powered detection device with a non-volatile memory
    • 具有非易失性存储器的自供电检测装置
    • US08422317B2
    • 2013-04-16
    • US12945168
    • 2010-11-12
    • David A. KampFilippo MarinelliThierry Roz
    • David A. KampFilippo MarinelliThierry Roz
    • G11C7/22G11C5/14
    • G08B13/06
    • The self-powered detection device comprises a Non-Volatile Memory (NVM) unit formed by at least a NVM cell and a sensor activated by a physical or chemical action or phenomenon, the NVM unit arranged for storing in the NVM cell, by using electrical power of the electrical stimulus pulse, a bit of information relative to detection by the sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal and a base terminal of the NVM unit with at least a given set voltage.
    • 所述自供电检测装置包括由至少NVM单元形成的非易失性存储器(NVM)单元和由物理或化学作用或现象激活的传感器,所述NVM单元被布置成存储在NVM单元中,通过使用电 电刺激脉冲的功率,在自动检测装置的检测模式期间相对于传感器检测的一点信息,至少一个物理或化学作用或现象至少具有给定的强度,或 并且产生在至少给定的设定电压之间提供在NVM单元的设定控制端子和基极端子之间的电压刺激信号。
    • 3. 发明申请
    • SELF-POWERED DETECTION DEVICE WITH A NON-VOLATILE MEMORY
    • 具有非易失性存储器的自动检测装置
    • US20110119017A1
    • 2011-05-19
    • US12945168
    • 2010-11-12
    • David A. KampFilippo MarinelliThierry Roz
    • David A. KampFilippo MarinelliThierry Roz
    • G06F15/00
    • G08B13/06
    • The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed by at least a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, the NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of the NVM unit with at least a given set voltage. In a first principal embodiment, the self-powered detection device comprises a read circuit (56) and a switch (58,60) arranged in the electrical path between the ground (GND) of the sensor and a terminal of the NVM cell and having its control gate (G) electrically connected to the set control terminal (SET), said switch being ON when its control gate receives in a detection mode said voltage stimulus signal and the self-powered detection device being arranged so that this switch is OFF in the read mode. In a second principal embodiment, a reset circuit is electrically connected in a reset mode to the base terminal (SET *) of the NVM unit for resetting said NVM cell and the self-powered detection device comprises a switch (58,60) arranged between the ground (GND) of the sensor and this base terminal and having its control gate (G) electrically connected to the set control terminal (SET), said switch being ON when its control gate receives in a detection mode said voltage stimulus signal and the self-powered detection device being arranged so that this switch is OFF in the reset mode.
    • 所述自供电检测装置包括由至少NVM单元形成的非易失性存储器(NVM)单元(52)和由物理或化学作用或现象激活的传感器,所述NVM单元被布置成存储在所述 NVM单元通过使用所述电刺激脉冲的电力,在自供电检测装置的检测模式期间相对于所述传感器的检测的一点信息,施加至少一个物理或化学作用或现象 它具有至少给定的强度或强度,并且导致在至少一个给定的设定电压之间提供在NVM单元的设定控制端(SET)和基端(SET *)之间的电压刺激信号。 在第一主要实施例中,自供电检测装置包括布置在传感器的接地(GND)和NVM单元的端子之间的电气路径中的读取电路(56)和开关(58,60),并具有 其控制栅极(G)电连接到设定控制端(SET),所述开关当其控制栅极在检测模式下接收所述电压刺激信号时,所述开关导通,并且所述自供电检测装置被布置成使得所述开关在 读取模式。 在第二主要实施例中,复位电路以复位模式电连接到NVM单元的基座(SET *),用于复位所述NVM单元,并且所述自供电检测装置包括布置在所述NVM单元之间的开关(58,60) 传感器的接地端(GND)和该基极端子,并且其控制栅极(G)电连接到设定控制端子(SET),当控制栅极在检测模式下接收时,所述开关导通,所述电压刺激信号和 自动供电的检测装置被布置成使得该复位模式下该开关为OFF。
    • 4. 发明申请
    • SELF-POWERED EVENT DETECTION DEVICE
    • 自供电事件检测装置
    • US20110115548A1
    • 2011-05-19
    • US12945138
    • 2010-11-12
    • David A. KampFilippo MarinelliThierry Roz
    • David A. KampFilippo MarinelliThierry Roz
    • G11C5/14
    • G08B13/06E05B39/00E05B45/06E05B51/023E05B67/22E05B2047/0058E05B2047/0062E05B2047/0064G08B29/181
    • The self-powered detection device comprises at least a non-volatile memory cell (24) and a sensor (16) which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, the memory cell being arranged for storing, by using the electrical power of said electrical stimulus pulse, at least a bit of information relative to the detection by the sensor of at least a first physical or chemical action or phenomenon applied to it with at least a given strength or intensity. The non-volatile memory cell is formed by a FET transistor (T1) having a control gate, a first diffusion (DRN) defining a first input and a second diffusion (SRC) defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode of this self-powered detection device, it receives on a set terminal, among said control gate and said first and second inputs, a voltage stimulus signal resulting from the first physical or chemical action or phenomenon. In a first embodiment of the invention, the set terminal of the FET transistor is its control gate and the first input of this FET transistor is connected to the ground of the sensor in said detection mode. In a further embodiment of the invention, the set terminal of the FET transistor is its first input and the control gate of this FET transistor is connected to the ground (GND) of the sensor in the detection mode.
    • 所述自供电检测装置至少包括由物理或化学作用或现象激活的非易失性存储器单元(24)和传感器(16),所述传感器形成能量收集器,所述能量收集器从所述物理或化学 动作或现象转换成电刺激脉冲,存储单元被布置成通过使用所述电刺激脉冲的电力来存储至少一点信息,所述信息相对于传感器至少检测第一物理或化学作用 或现象,至少具有给定的强度或强度。 非易失性存储单元由具有控制栅极的FET晶体管(T1),限定第一输入的第一扩散(DRN)和限定第二输入的第二扩散(SRC)形成。 当该自供电检测装置的检测模式在所述控制栅极和所述第一和第二输入端之间的设定端子上接收时,将该FET晶体管从其初始逻辑状态设定为其写入的逻辑状态, 由第一次物理或化学作用或现象引起的信号。 在本发明的第一实施例中,FET晶体管的设置端子是其控制栅极,并且该FET晶体管的第一输入端以所述检测模式连接到传感器的接地。 在本发明的又一个实施例中,FET晶体管的设置端是其第一输入,并且该FET晶体管的控制栅极在检测模式下连接到传感器的地(GND)。
    • 5. 发明申请
    • Array of non volatile split-gate memory cells for avoiding parasitic programming and programming method thereof
    • 用于避免寄生编程及其编程方法的非易失性分闸存储器单元阵列
    • US20050018504A1
    • 2005-01-27
    • US10896911
    • 2004-07-23
    • Filippo MarinelliNadia Narabech
    • Filippo MarinelliNadia Narabech
    • G11C11/34G11C16/04G11C16/10G11C16/34
    • G11C16/0425G11C16/10G11C16/3418
    • There is disclosed an array (10) of split-gate non-volatile memory cells (24) supplied with power at a low voltage (VDD) by a power supply (30), said cells being arranged in one or more rows and columns and electrically interconnected in groups to form one or more pages (12). The array comprises control logic (32) delivering a defined programming voltage (VPROG) that is close or or substantially equal to the low power supply voltage that is applied to a control gate (245) of at least one cell (24A) that is to be programmed via a word control line (18) corresponding to that cell and blocking logic (36) delivering a first blocking voltage (VBLOC1) that is greater than said low power supply voltage and is applied to the first regions (241) of the cells (24B) sharing the same word control line (18) as said cell that is to be programmed via a bit control line (22) corresponding to those cells.
    • 公开了一种通过电源(30)以低电压(VDD)供电的分离栅极非易失性存储单元(24)的阵列(10),所述单元被布置成一行或多行和列,并且 以组形式电互连以形成一个或多个页面(12)。 所述阵列包括控制逻辑(32),其输送接近或或基本上等于施加到至少一个单元(24A)的控制栅极(245)的所述低电源电压的定义编程电压(VPROG),所述至少一个单元 通过与该单元相对应的字控制线(18)来编程,并且阻塞逻辑(36)传送大于所述低电源电压的第一阻断电压(VBLOC1),并被施加到单元的第一区(241) (24B)与通过与这些单元相对应的位控制线(22)编程的所述单元共享相同的字控制线(18)。