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1. 发明授权

US5101478A I/O structure for information processing system 失效
标题翻译：信息处理系统的I / O结构
公开(公告)号：US5101478A
公开(公告)日：1992-03-31
申请号：US228768
申请日：1988-08-04
申请人： Andrew N. Fu , Tom R. Kibler , James B. MacDonald , Robert C. Nash , Stephen W. Olson , Bhikoo J. Patel , Robert R. Trottier , Kevin T. Mahoney , David L. Whipple , Peter A. Morrison
发明人： Andrew N. Fu , Tom R. Kibler , James B. MacDonald , Robert C. Nash , Stephen W. Olson , Bhikoo J. Patel , Robert R. Trottier , Kevin T. Mahoney , David L. Whipple , Peter A. Morrison
IPC分类号： G06F13/12
CPC分类号： G06F13/126
摘要： An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components. The communications to SPUs all require a single SPU bus cycle; the communications to system components require one or more cycles. The system bus interface translates communications to system components into communications on the system bus and translates communications on the system bus intended for a SPU into communications to SPUs. The SPU bus includes first lines for carrying an I/O command and an identifier for an SPU involved in the communication and second lines for carrying the contents of the communication. In multicycle communications, the I/O command and identifier remain on the first lines for all cycles, but the information on the second lines varies from cycle to cycle.
摘要翻译：一种用于数字数据处理系统的I / O结构，其中包括处理器和系统存储器在内的系统组件通过系统总线连接。 I / O结构包括连接到系统总线的系统总线接口，连接到系统总线接口的同步卫星处理单元（SPU）总线，连接到SPU总线的一个或多个卫星处理单元（SPU）和外围设备附属于卫星处理单元。每个SPU具有三个主要部分：包括用于控制SPU的微处理器的控制逻辑，用于控制外围设备并在外围设备和SPU之间传送数据的外围设备专用的设备适配器，以及连接到控制逻辑的接口单元以及用于向SPU总线提供I / O通信并响应SPU总线上的I / O通信的设备适配器。 I / O通信分为两类：与SPU的通信和与系统组件的通信。与SPU的通信都需要单个SPU总线周期; 与系统组件的通信需要一个或多个周期。系统总线接口将系统组件的通信转换为系统总线上的通信，并将用于SPU的系统总线上的通信转换为与SPU通信。 SPU总线包括用于承载I / O命令的第一行和用于通信中涉及的SPU的标识符和用于承载通信内容的第二行。在多循环通信中，I / O命令和标识符保留在所有周期的第一行上，但是第二行的信息随周期而不同。

2. 发明授权

US5123108A Improved CPU pipeline having register file bypass and working register bypass on update/access address compare 失效
标题翻译：改进的CPU管道具有寄存器文件旁路和工作寄存器旁路更新/访问地址比较
公开(公告)号：US5123108A
公开(公告)日：1992-06-16
申请号：US405794
申请日：1989-09-11
申请人： Stephen W. Olson , James B. MacDonald
发明人： Stephen W. Olson , James B. MacDonald
IPC分类号： G06F9/38 , G06F9/302 , G06F13/42
CPC分类号： G06F9/3826 , G06F9/3824
摘要： An A output and a B output of a register file 16 are each provided to an associated multiplexer (18,20). Each multiplexer has as a further input a bus (CB00:31) that conveys a result from an ALU 22 via an ALU shifter 28. Outputs of the multiplexers are provided to corresponding A or B inputs of the ALU. Each multiplexer is controlled by an associated register file address comparator (24,26). The address comparators each have as an input corresponding register file A and B update and access addresses. The address comparators compare their associated register file update and access addresses to determine if the register file register selected for access is equal to the register file register selected for update. If these two addresses are found to be equal it is indicated that the result of an ALU operation during an instruction cycle N is to be used as an operand for an ALU operation during a cycle N+1. When this condition is detected the output of the associated address comparator enables the corresponding multiplexer select input to gate the ALU result directly to the corresponding input of the ALU, thereby effectively bypassing the register file.
摘要翻译：寄存器文件16的A输出和B输出分别被提供给相关联的多路复用器（18,20）。每个多路复用器具有作为另一输入的总线（CB00：31），其通过ALU移位器28从ALU22传送结果。多路复用器的输出被提供给ALU的对应的A或B输入。每个复用器由相关联的寄存器文件地址比较器（24,26）控制。地址比较器各自具有对应的寄存器文件A和B更新和访问地址的输入。地址比较器比较其关联的寄存器文件更新和访问地址，以确定选择进行访问的寄存器文件寄存器是否等于选择进行更新的寄存器文件寄存器。如果发现这两个地址相等，则指示在指令周期N期间的ALU操作的结果将用作在周期N + 1期间的ALU操作的操作数。当检测到该条件时，相关地址比较器的输出使相应的多路复用器选择输入能够直接将ALU结果门控到ALU的相应输入，从而有效地绕过寄存器文件。

3. 发明授权

US5479628A Virtual address translation hardware assist circuit and method 失效
标题翻译：虚拟地址转换硬件辅助电路及方法
公开(公告)号：US5479628A
公开(公告)日：1995-12-26
申请号：US135037
申请日：1993-10-12
申请人： Stephen W. Olson , James B. MacDonald , Richard W. Lones
发明人： Stephen W. Olson , James B. MacDonald , Richard W. Lones
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/10
摘要： A method, and circuitry that operates in accordance with the method, for generating an entry for a translation buffer in a data processor that employs virtual memory addressing. The method includes the first steps of storing a Faulted Virtual Address in a first register (96) and a Zone Table Address (ZTA) in a second register (94). In response to the execution of a micro-instruction, a next step forms an address in memory of a Zone Table Entry (ZTE) by selectively combining a first portion of the content of the first register with the content of the second register, while simultaneously testing the ZTA for physical address mapping. In response to an execution of a next micro-instruction, a next step accesses the ZTE with the formed address, and forms an address in memory of a Segment Table Entry (STE) by selectively combining a second portion the content of the first register with a content of the ZTE, while simultaneously testing the ZTE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the STE with the formed address, and forms an address in memory of a Page Table Entry (PTE) by selectively combining a third portion of the content of the first register with a content of the STE, while simultaneously testing the STE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the PTE with the formed address and selectively combines the content of the STE with the content of the PTE and outputs the combination as the translation buffer entry, while simultaneously testing the PTE for a Page fault.
摘要翻译：一种根据该方法操作的方法和电路，用于在采用虚拟存储器寻址的数据处理器中生成翻译缓冲器的条目。该方法包括在第二寄存器（94）中的第一寄存器（96）和区域表地址（ZTA）中存储故障虚拟地址的第一步骤。响应于微指令的执行，下一步通过选择性地组合第一寄存器的内容的第一部分和第二寄存器的内容，同时形成区域表条目（ZTE）的存储器中的地址测试ZTA的物理地址映射。响应于下一个微指令的执行，下一个步骤以形成的地址访问中兴，并且通过有选择地将第一个寄存器的内容的第二部分与中兴通讯的内容，同时测试中兴区域的故障。响应于下一个微指令的执行，下一个步骤以形成的地址访问STE，并且通过有选择地组合第一寄存器的内容的第三部分来形成页表项（PTE）的存储器中的地址具有STE的内容，同时测试STE的区域故障。响应于下一个微指令的执行，下一个步骤使用形成的地址访问PTE，并选择性地将STE的内容与PTE的内容组合，并输出组合作为转换缓冲区条目，同时测试 PTE为页面错误。

4. 发明授权

US5668967A Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency 失效
标题翻译：用于将读 - 修改 - 写周期数减少到存储器并提高DMA效率的装置和方法
公开(公告)号：US5668967A
公开(公告)日：1997-09-16
申请号：US303853
申请日：1994-09-09
申请人： Stephen W. Olson , James B. MacDonald , Edward D. Mann , James W. Petersen, Jr.
发明人： Stephen W. Olson , James B. MacDonald , Edward D. Mann , James W. Petersen, Jr.
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register. The transfer is then begun and all incoming IO read addresses are checked for a current quad-word compare. If an incoming quad-word aligned IO read address is not equal to the content of the IO previous address register, a memory read request is generated using the incremented address, and the MDU read data registers are advanced. A feature of this invention is that no specific addresses are used, and a knowledge of a transfer width (byte, word, etc.) is not required to determine memory operation types.
摘要翻译：公开了用于将中央处理器（12）（CP）和IO控制器（30）（IOC）连接到主存储器（40）的方法和装置。 CP和IO写入缓冲器各自包括位于一对存储器数据单元（MDU）集成电路（38a，38b）中的一对存储器输入数据寄存器，以及两个存储器地址寄存器，前一个存储器地址寄存器和地址比较器，位于存储器地址单元（MAU）（36）中。这些寄存器结合相关的控制逻辑，用于将CP和IO写入地址和数据缓冲到主存储器。如果两个地址寄存器都有待处理的写入，则使用先前的地址寄存器和比较器，检查最后加载的地址寄存器与当前写入地址的匹配。使用MDU内的写入合并电路，匹配导致先前的写入数据和当前的写入数据组合成一个挂起的写入。通过首先将第一个IO地址寄存器中的四字对齐地址指定的存储单元的读取数据加载到MDU读取数据寄存器中，然后在第二个IO地址寄存器中加载四字对齐的地址，从而执行IO读取操作。然后开始传输，并检查所有输入的IO读取地址以获得当前的四字比较。如果输入的四字对齐IO读地址不等于IO先前地址寄存器的内容，则使用增加的地址生成存储器读请求，并且MDU读数据寄存器被提前。本发明的一个特征是没有使用特定的地址，并且不需要知道传输宽度（字节，字等）来确定存储器操作类型。

5. 发明授权

US5377338A Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency 失效
标题翻译：用于将读 - 修改 - 写周期数减少到存储器并提高DMA效率的装置和方法
公开(公告)号：US5377338A
公开(公告)日：1994-12-27
申请号：US134806
申请日：1993-10-12
申请人： Stephen W. Olson , James B. MacDonald , Edward D. Mann , James W. Petersen, Jr.
发明人： Stephen W. Olson , James B. MacDonald , Edward D. Mann , James W. Petersen, Jr.
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register. The transfer is then begun and all incoming IO read addresses are checked for a current quad-word compare. If an incoming quad-word aligned IO read address is not equal to the content of the IO previous address register, a memory read request is generated using the incremented address, and the MDU read data registers are advanced. A feature of this invention is that no specific addresses are used, and a knowledge of a transfer width (byte, word, etc.) is not required to determine memory operation types.
摘要翻译：公开了用于将中央处理器（12）（CP）和IO控制器（30）（IOC）连接到主存储器（40）的方法和装置。 CP和IO写入缓冲器各自包括位于一对存储器数据单元（MDU）集成电路（38a，38b）中的一对存储器输入数据寄存器，以及两个存储器地址寄存器，前一个存储器地址寄存器和地址比较器，位于存储器地址单元（MAU）（36）中。这些寄存器结合相关的控制逻辑，用于将CP和IO写入地址和数据缓冲到主存储器。如果两个地址寄存器都有待处理的写入，则使用先前的地址寄存器和比较器，检查最后加载的地址寄存器与当前写入地址的匹配。使用MDU内的写入合并电路，匹配导致先前的写入数据和当前的写入数据组合成一个挂起的写入。通过首先将第一个IO地址寄存器中的四字对齐地址指定的存储单元的读取数据加载到MDU读取数据寄存器中，然后在第二个IO地址寄存器中加载四字对齐的地址，从而执行IO读取操作。然后开始传输，并检查所有输入的IO读取地址以获得当前的四字比较。如果输入的四字对齐IO读地址不等于IO先前地址寄存器的内容，则使用增加的地址生成存储器读请求，并且MDU读数据寄存器被提前。本发明的一个特征是没有使用特定的地址，并且不需要知道传输宽度（字节，字等）来确定存储器操作类型。

6. 发明授权

US5495422A Method for combining a plurality of independently operating circuits within a single package 失效
标题翻译：用于在单个封装内组合多个独立操作电路的方法
公开(公告)号：US5495422A
公开(公告)日：1996-02-27
申请号：US134809
申请日：1993-10-12
申请人： Stephen W. Olson
发明人： Stephen W. Olson
IPC分类号： G06F1/22 , H01L27/118 , H03K19/173
CPC分类号： G06F1/22 , H01L27/11898 , H03K19/1732
摘要： An integrated circuit has a plurality of interface pins and includes a first circuit block that is comprised of a plurality of gate-equivalent circuits; the first circuit block being a first partition of a data processing system. The integrated circuit further includes at least one other circuit block comprised of a plurality of gate-equivalent circuits; the second circuit block being a second partition of the data processing system. The first and second circuit blocks are capable of operating independently of one another, with each performing an associated function. At least one mode select interface pin is provided, in conjunction with gating circuitry that is interposed between the first and second circuit blocks and the interface pins for selectively coupling, in accordance with a logic level applied to the at least one mode select interface pin, only one of the circuit blocks to the interface pins. A method of specifying a gate array integrated circuit to include a plurality of independently operating circuit blocks is also disclosed.
摘要翻译：集成电路具有多个接口引脚，并且包括由多个栅极等效电路组成的第一电路块; 第一电路块是数据处理系统的第一分区。集成电路还包括由多个栅极等效电路组成的至少一个其它电路块; 第二电路块是数据处理系统的第二分区。第一和第二电路块能够彼此独立地操作，每个执行相关联的功能。提供至少一个模式选择接口引脚，结合根据施加到至少一个模式选择接口引脚的逻辑电平插入在第一和第二电路块之间的门控电路和用于选择性地耦合的接口引脚，只有一个电路块到接口引脚。还公开了一种指定门阵列集成电路以包括多个独立操作的电路块的方法。

7. 发明申请

US20120325469A1 PROCESS AND SYSTEM FOR TREATING PRODUCED WATER AND FLOWBACK WATER FROM OIL AND GAS OPERATIONS 审中-公开
标题翻译：用于处理石油和天然气运行中生产的水和流动水的方法和系统
公开(公告)号：US20120325469A1
公开(公告)日：2012-12-27
申请号：US13533632
申请日：2012-06-26
申请人： Stephen W. Olson , Benjamin R. Earl , Daniel N. Ziol
发明人： Stephen W. Olson , Benjamin R. Earl , Daniel N. Ziol
IPC分类号： E21B43/40 , E21B21/06
CPC分类号： E21B43/40 , C02F1/42 , C02F1/5245 , C02F1/66 , C02F9/00 , C02F2101/006 , C02F2101/101 , C02F2101/203 , C02F2101/206 , C02F2101/32 , C02F2103/10 , C02F2201/007 , C02F2303/16
摘要： A system and method for treatment of flowback water and produced water at an oil or gas wellhead includes a modular treatment facility that may be installed at a well site. The modular treatment facility includes separate and interchangeable modules that remove undesirable contaminants. The modules may be removed and replaced with similar modules when they are no longer effective at removing the contaminants. The spent modules may be transported to a regeneration center to be regenerated and transported back to a modular treatment facility.
摘要翻译：用于处理油或气井口的回流水和生产水的系统和方法包括可以安装在井场的模块化处理设施。模块化处理设施包括分离和可互换的模块，可以去除不需要的污染物。当模块不再有效地去除污染物时，模块可以被移除并且被类似的模块替换。废弃的模块可以被运送到再生中心以再生并被运送回到模块化处理设施。

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