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1. 发明授权

US5668967A Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency 失效
标题翻译：用于将读 - 修改 - 写周期数减少到存储器并提高DMA效率的装置和方法
公开(公告)号：US5668967A
公开(公告)日：1997-09-16
申请号：US303853
申请日：1994-09-09
申请人： Stephen W. Olson , James B. MacDonald , Edward D. Mann , James W. Petersen, Jr.
发明人： Stephen W. Olson , James B. MacDonald , Edward D. Mann , James W. Petersen, Jr.
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register. The transfer is then begun and all incoming IO read addresses are checked for a current quad-word compare. If an incoming quad-word aligned IO read address is not equal to the content of the IO previous address register, a memory read request is generated using the incremented address, and the MDU read data registers are advanced. A feature of this invention is that no specific addresses are used, and a knowledge of a transfer width (byte, word, etc.) is not required to determine memory operation types.
摘要翻译：公开了用于将中央处理器（12）（CP）和IO控制器（30）（IOC）连接到主存储器（40）的方法和装置。 CP和IO写入缓冲器各自包括位于一对存储器数据单元（MDU）集成电路（38a，38b）中的一对存储器输入数据寄存器，以及两个存储器地址寄存器，前一个存储器地址寄存器和地址比较器，位于存储器地址单元（MAU）（36）中。这些寄存器结合相关的控制逻辑，用于将CP和IO写入地址和数据缓冲到主存储器。如果两个地址寄存器都有待处理的写入，则使用先前的地址寄存器和比较器，检查最后加载的地址寄存器与当前写入地址的匹配。使用MDU内的写入合并电路，匹配导致先前的写入数据和当前的写入数据组合成一个挂起的写入。通过首先将第一个IO地址寄存器中的四字对齐地址指定的存储单元的读取数据加载到MDU读取数据寄存器中，然后在第二个IO地址寄存器中加载四字对齐的地址，从而执行IO读取操作。然后开始传输，并检查所有输入的IO读取地址以获得当前的四字比较。如果输入的四字对齐IO读地址不等于IO先前地址寄存器的内容，则使用增加的地址生成存储器读请求，并且MDU读数据寄存器被提前。本发明的一个特征是没有使用特定的地址，并且不需要知道传输宽度（字节，字等）来确定存储器操作类型。

2. 发明授权

US5377338A Apparatus and methods for reducing numbers of read-modify-write cycles to a memory, and for improving DMA efficiency 失效
标题翻译：用于将读 - 修改 - 写周期数减少到存储器并提高DMA效率的装置和方法
公开(公告)号：US5377338A
公开(公告)日：1994-12-27
申请号：US134806
申请日：1993-10-12
申请人： Stephen W. Olson , James B. MacDonald , Edward D. Mann , James W. Petersen, Jr.
发明人： Stephen W. Olson , James B. MacDonald , Edward D. Mann , James W. Petersen, Jr.
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs. IO read operations are performed by first loading the MDU read data registers with read data from memory locations specified by a quad-word aligned address in the first IO address register, followed by an incremented quad-word aligned address in the second IO address register. The transfer is then begun and all incoming IO read addresses are checked for a current quad-word compare. If an incoming quad-word aligned IO read address is not equal to the content of the IO previous address register, a memory read request is generated using the incremented address, and the MDU read data registers are advanced. A feature of this invention is that no specific addresses are used, and a knowledge of a transfer width (byte, word, etc.) is not required to determine memory operation types.
摘要翻译：公开了用于将中央处理器（12）（CP）和IO控制器（30）（IOC）连接到主存储器（40）的方法和装置。 CP和IO写入缓冲器各自包括位于一对存储器数据单元（MDU）集成电路（38a，38b）中的一对存储器输入数据寄存器，以及两个存储器地址寄存器，前一个存储器地址寄存器和地址比较器，位于存储器地址单元（MAU）（36）中。这些寄存器结合相关的控制逻辑，用于将CP和IO写入地址和数据缓冲到主存储器。如果两个地址寄存器都有待处理的写入，则使用先前的地址寄存器和比较器，检查最后加载的地址寄存器与当前写入地址的匹配。使用MDU内的写入合并电路，匹配导致先前的写入数据和当前的写入数据组合成一个挂起的写入。通过首先将第一个IO地址寄存器中的四字对齐地址指定的存储单元的读取数据加载到MDU读取数据寄存器中，然后在第二个IO地址寄存器中加载四字对齐的地址，从而执行IO读取操作。然后开始传输，并检查所有输入的IO读取地址以获得当前的四字比较。如果输入的四字对齐IO读地址不等于IO先前地址寄存器的内容，则使用增加的地址生成存储器读请求，并且MDU读数据寄存器被提前。本发明的一个特征是没有使用特定的地址，并且不需要知道传输宽度（字节，字等）来确定存储器操作类型。

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