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1. 发明授权

US06252234B1 Reaction force isolation system for a planar motor 有权
标题翻译：平面电机的反作用力隔离系统
公开(公告)号：US06252234B1
公开(公告)日：2001-06-26
申请号：US09134278
申请日：1998-08-14
申请人： Andrew J. Hazelton , Keiichi Tanaka , Yutaka Hayashi , Nobukazu Ito
发明人： Andrew J. Hazelton , Keiichi Tanaka , Yutaka Hayashi , Nobukazu Ito
IPC分类号： G01F2300
CPC分类号： G03F7/70358 , F16F15/02 , G03F7/70716 , G03F7/70758 , G03F7/70833 , G03F7/709
摘要： The present invention provides a structure for isolating the reaction forces generated by a planar motor. Specifically, the fixed portion of the reaction motor, which is subject to reaction forces, is structurally isolated from the rest of the system in which the planar motor is deployed. In accordance with one embodiment of the present invention, the fixed portion of the planar motor is separated from the rest of the system and coupled to ground. The rest of the system is isolated from ground by deploying vibration isolation means. Alternatively or in addition, the fixed portion of the planar motor may be structured to move (e.g., on bearings) in the presence of reaction forces, so as to absorb the reaction forces with its inertia. In a further embodiment of the present invention, the fixed portion of the planar motor and the article to be moved are supported by the same frame, with the fixed portion of the planar motor movable on bearings.
摘要翻译：本发明提供了用于隔离由平面电动机产生的反作用力的结构。具体地，反应电动机的受到反作用力的固定部分与其中布置有平面电动机的系统的其余部分结构地隔离。根据本发明的一个实施例，平面电动机的固定部分与系统的其余部分分离并耦合到地面。系统的其余部分通过部署隔振装置与地面隔离。或者或另外，平面电动机的固定部分可以被构造成在反作用力的存在下移动（例如，在轴承上），以便以其惯性吸收反作用力。在本发明的另一实施例中，平面电动机的固定部分和待移动的物品由相同的框架支撑，平面电动机的固定部分可在轴承上移动。

2. 发明申请

US20050218470A1 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US20050218470A1
公开(公告)日：2005-10-06
申请号：US11087587
申请日：2005-03-24
申请人： Hiroaki Ohkubo , Yasutaka Nakashiba , Naoyoshi Kawahara , Hiroshi Murase , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
发明人： Hiroaki Ohkubo , Yasutaka Nakashiba , Naoyoshi Kawahara , Hiroshi Murase , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
IPC分类号： H01L21/3205 , G01K7/01 , G01K7/18 , G01K7/22 , G01K7/42 , H01L21/822 , H01L21/8234 , H01L23/34 , H01L23/48 , H01L23/52 , H01L23/58 , H01L27/04 , H01L27/06 , H01L29/00 , H01L31/058 , H05B1/02
CPC分类号： H01L23/34 , G01K7/01 , G01K7/42 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device, a logic circuit section is provided at the top surface of a P-type silicon substrate and a multi-level wiring layer. The device is further provided with a temperature sensor section in which a first temperature monitor member of vanadium oxide is provided above the multi-level wiring layer. A second temperature monitor member of Ti is provided at a lowermost layer of the multi-level wiring layer. The first and second temperature monitor members are connected in series between a ground potential wire and a power-source potential wire, with an output terminal connected to the node of both members. The temperature coefficient of the electric resistivity of the first temperature monitor member is negative, while that of the second temperature monitor member is positive.
摘要翻译：在半导体集成电路器件中，逻辑电路部分设置在P型硅衬底和多层布线层的顶表面处。该装置还设置有温度传感器部分，其中在多层布线层上方设置有氧化钒的第一温度监测部件。 Ti的第二温度监视器构件设置在多层布线层的最下层。第一和第二温度监视器构件串联连接在地电位线和电源电位线之间，输出端连接到两个构件的节点。第一温度监视部件的电阻率的温度系数为负，第二温度监视部件的温度系数为正。

3. 发明申请

US20050221573A1 Integrated circuit device, method of manufacturing the same and method of forming vanadium oxide film 失效
标题翻译：集成电路器件及其制造方法以及形成氧化钒膜的方法
公开(公告)号：US20050221573A1
公开(公告)日：2005-10-06
申请号：US11086743
申请日：2005-03-23
申请人： Naoyoshi Kawahara , Hiroshi Murase , Hiroaki Ohkubo , Yasutaka Nakashiba , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
发明人： Naoyoshi Kawahara , Hiroshi Murase , Hiroaki Ohkubo , Yasutaka Nakashiba , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/316 , H01L21/3213 , H01L21/822 , H01L21/8234 , H01L23/522 , H01L27/04 , H01L37/00 , H01L47/00
CPC分类号： H01L21/02192 , H01L21/022 , H01L21/31604 , H01L23/5228 , H01L28/24 , H01L37/00 , H01L2924/0002 , H01L2924/00
摘要： A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.
摘要翻译：在层间绝缘层上形成氧化钒膜，依次在氧化钒膜上形成氧化硅膜和氮化硅膜。用抗蚀剂图案作为掩模，对氮化硅膜进行图案化。然后，使用剥离溶液或氧等离子体灰化除去抗蚀剂图案。接下来，利用图案化的氮化硅膜作为掩模，氧化硅膜和氧化钒膜被蚀刻以形成氧化钒的电阻膜。

4. 发明授权

US06512281B2 Method of forming a semiconductor device and an improved deposition system 失效
标题翻译：形成半导体器件和改进的沉积系统的方法
公开(公告)号：US06512281B2
公开(公告)日：2003-01-28
申请号：US09919389
申请日：2001-07-31
申请人： Nobukazu Ito
发明人： Nobukazu Ito
IPC分类号： H01L27095
CPC分类号： H01L21/76873 , C23C14/042 , C23C14/50 , C23C14/568 , C25D7/123 , C25D17/001 , H01L21/2855 , H01L21/2885 , H01L21/76841 , H01L21/76843
摘要： A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the same metal as the seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.
摘要翻译：一种在绝缘层上形成多层结构的方法包括以下步骤：通过使用第一沉积掩模在绝缘层的预定区域上选择性地沉积阻挡层; 通过使用第二沉积掩模选择性地沉积由物质与阻挡层不同的金属制成的金属种子层，使得金属种子层不仅在阻挡层的整个表面上延伸，而且延伸到位于在绝缘层的预定区域之外; 并且形成与种子层相同的金属制成的金属镀层，使得金属镀层附着在金属种子层上，由此金属镀层与阻挡层以及绝缘层分离。

5. 发明授权

US07777288B2 Integrated circuit device and fabrication method therefor 有权
标题翻译：集成电路器件及其制造方法
公开(公告)号：US07777288B2
公开(公告)日：2010-08-17
申请号：US11052215
申请日：2005-02-08
申请人： Naoyoshi Kawahara , Hiroshi Murase , Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
发明人： Naoyoshi Kawahara , Hiroshi Murase , Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
IPC分类号： H01L31/058
CPC分类号： H01C7/1013 , H01L27/16 , H01L2924/0002 , H01L2924/00
摘要： In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.
摘要翻译：在半导体集成电路器件的温度传感器部分中，形成多层布线结构的最上层布线层的布线。在两条电线之间设置氧化钒的片状温度监视元件，以覆盖两条电线。因此，温度监视元件通过两个通孔和最上面布线层的两条导线连接在多层布线结构的底层布线层的两条导线之间。

6. 发明申请

US20050161822A1 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US20050161822A1
公开(公告)日：2005-07-28
申请号：US11038094
申请日：2005-01-21
申请人： Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoyoshi Kawahara , Hiroshi Murase , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
发明人： Hiroaki Ohkubo , Kuniko Kikuta , Yasutaka Nakashiba , Naoyoshi Kawahara , Hiroshi Murase , Naoki Oda , Tokuhito Sasaki , Nobukazu Ito
IPC分类号： G01K1/14 , G01K7/00 , G01K7/01 , H01L21/4763 , H01L21/822 , H01L23/00 , H01L23/34 , H01L23/48 , H01L23/522 , H01L27/02 , H01L27/04 , H01L27/06 , H01L37/00
CPC分类号： H01L23/34 , G01K7/015 , H01L23/522 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.
摘要翻译：在半导体集成电路器件的温度传感器部分中，在多层布线层的最上层形成钨的第一通孔，并且在覆盖通孔的多层布线层的区域上设置钛焊盘。以覆盖多层布线层和焊盘的方式设置绝缘层，第二通孔形成为到达焊盘。通过反应性溅射将氧化钒埋在第二通孔中，并且以使得第二通孔彼此连接的方式提供氧化钒的温度监视部分。因此，温度监视器部分连接在两条线之间。

7. 发明授权

US06573607B2 Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US06573607B2
公开(公告)日：2003-06-03
申请号：US09939396
申请日：2001-08-24
申请人： Nobukazu Ito , Yoshihisa Matsubara
发明人： Nobukazu Ito , Yoshihisa Matsubara
IPC分类号： H01L2348
CPC分类号： H01L21/76888 , H01L21/321 , H01L21/76807 , H01L23/53238 , H01L2924/0002 , Y10S438/976 , H01L2924/00
摘要： There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/min or less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

8. 发明授权

US06465354B1 Method of improving the planarization of wiring by CMP 失效
标题翻译：通过CMP改善布线平面化的方法
公开(公告)号：US06465354B1
公开(公告)日：2002-10-15
申请号：US09435612
申请日：1999-11-08
申请人： Kazumi Sugai , Nobukazu Ito , Hiroaki Tachibana
发明人： Kazumi Sugai , Nobukazu Ito , Hiroaki Tachibana
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , H01L21/7684 , H01L21/76877
摘要： A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of ‘Erosion’ to be prevented, as well as it is capable of being prevented occurrence of ‘micro-scratch’ on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200° C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.
摘要翻译：包括布线致密部分和布线隔离部分的半导体器件的制造方法能够防止“侵蚀”的发生，并且能够防止在氧化物层的表面上发生“微划痕”。在形成由铜组成的金属镀层之前，制造方法在绝缘层上设置多个沟槽部分以嵌入沟槽部分。制造工序以布线致密部中的金属镀层的粒径变得小于配线隔离部的晶粒尺寸的方式进行退火。例如，退火的基板温度为70〜200℃。随后，制造步骤在抛光金属镀层的同时使半导体器件完美化，使基板的表面平坦。

9. 发明授权

US06372114B1 Method of forming a semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US06372114B1
公开(公告)日：2002-04-16
申请号：US09288265
申请日：1999-04-08
申请人： Nobukazu Ito
发明人： Nobukazu Ito
IPC分类号： C25D502
CPC分类号： H01L21/76873 , C23C14/042 , C23C14/50 , C23C14/568 , C25D7/123 , C25D17/001 , H01L21/2855 , H01L21/2885 , H01L21/76841 , H01L21/76843
摘要： A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a first deposition mask; selectively depositing a metal seed layer made of a metal which is different in substance from the barrier layer by use of a second deposition mask, so that the metal seed layer extends not only on an entire surface of the barrier layer but also a peripheral region positioned outside the predetermined region of the insulating layer; and forming a metal plating layer made of the metal of the metal seed layer, so that the metal plating layer is adhered on the metal seed layer whereby the metal plating layer is separated from the barrier layer and also from the insulating layer.
摘要翻译：一种在绝缘层上形成多层结构的方法包括以下步骤：通过使用第一沉积掩模在绝缘层的预定区域上选择性地沉积阻挡层; 通过使用第二沉积掩模选择性地沉积由物质与阻挡层不同的金属制成的金属种子层，使得金属种子层不仅在阻挡层的整个表面上延伸，而且延伸到位于在绝缘层的预定区域之外; 以及形成由所述金属种子层的金属制成的金属镀层，使得所述金属镀层附着在所述金属种子层上，由此所述金属镀层与所述阻挡层以及所述绝缘层分离。

10. 发明授权

US06309970B1 Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface 失效
标题翻译：在暴露的铜表面形成多层铜互连形成铜氧化物的方法
公开(公告)号：US06309970B1
公开(公告)日：2001-10-30
申请号：US09385756
申请日：1999-08-30
申请人： Nobukazu Ito , Yoshihisa Matsubara
发明人： Nobukazu Ito , Yoshihisa Matsubara
IPC分类号： H01L2144
CPC分类号： H01L21/76888 , H01L21/321 , H01L21/76807 , H01L23/53238 , H01L2924/0002 , Y10S438/976 , H01L2924/00
摘要： There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/minor less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.
摘要翻译：提出了包括多层铜互连的半导体器件; 其中对应于另一铜互连层的至少一个下层的铜互连的表面通过以20nm /次要的较小的氧化速率进行氧化而变成氧化铜至30nm或更大的厚度，从而反射在通过光刻法形成沟槽以形成通过镶嵌形成铜互连的情况下，防止来自下级铜互连的曝光光。

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