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    • 1. 发明授权
    • Gated counter analog-to-digital converter with error correction
    • 具有纠错功能的门控模数转换器
    • US06452520B1
    • 2002-09-17
    • US09725620
    • 2000-11-29
    • Andrew D. SmithQuentin P. HerrMark W. JohnsonBruce J. Dalrymple
    • Andrew D. SmithQuentin P. HerrMark W. JohnsonBruce J. Dalrymple
    • H03M100
    • H03M1/0602H03M1/60
    • A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter (50) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system (70) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter (10) to take into account the non-linearities of the primary quantizer (30).
    • 超导A / D转换器(10)具有用于消除主量化器(30)中的非线性的误差校正系统(70)。 转换器(10)包括主量化器(30),主SFQ计数器(50)和纠错系统(70)。 主量化器(30)基于模拟输入信号的平均电压产生初始SFQ脉冲。 主SFQ计数器(50)基于主SFQ脉冲的频率将初级SFQ脉冲转换成数字输出信号。 误差校正系统(70)根据模拟输入信号和初级SFQ脉冲校正数字输出信号。 使用主SFQ脉冲来校正数字输出信号允许转换器(10)考虑主量化器(30)的非线性。
    • 4. 发明授权
    • High-sensitivity, self-clocked receiver for multi-chip superconductor circuits
    • 用于多芯片超导体电路的高灵敏度,自定时接收器
    • US06420895B1
    • 2002-07-16
    • US09815810
    • 2001-03-23
    • Quentin P. HerrMark W. Johnson
    • Quentin P. HerrMark W. Johnson
    • H03K19195
    • H03K3/38H03K19/195H04L7/0008H04L7/0276
    • A receiver (50) for providing chip-to-chip communication in a superconductor integrated circuit. The receiver (50) includes a detector circuit (52) for asynchronously receiving an input current, a splitter circuit (60) connected to the detector circuit (52) for generating first and second signals, a delay circuit (62) receiving the second signal from the splitter circuit for generating a delayed signal and a register circuit (64) receiving the first signal from the splitter circuit (60) and the delayed signal from the delay circuit (62) for producing a single flux quantum (SFQ) pulse. The receiver (50) according to the present invention provides an asynchronous chip-to-chip communication between a multi-chip superconductive circuit having low input current without an external rf clock.
    • 一种用于在超导体集成电路中提供芯片到芯片通信的接收器(50)。 接收器(50)包括用于异步接收输入电流的检测器电路(52),连接到检测器电路(52)的分离器电路(60),用于产生第一和第二信号;延迟电路(62),接收第二信号 从用于产生延迟信号的分路器电路和从分路器电路(60)接收第一信号的寄存器电路(64)和来自延迟电路(62)的延迟信号用于产生单通量量(SFQ)脉冲。 根据本发明的接收机(50)提供具有低输入电流的多芯片超导电路之间的异步芯片到芯片通信,而没有外部rf时钟。
    • 5. 发明授权
    • Single flux quantum series biasing technique using superconducting DC transformer
    • 使用超导直流变压器的单通量子量子偏置技术
    • US06483339B1
    • 2002-11-19
    • US09935310
    • 2001-08-22
    • Dale J. DurandQuentin P. HerrMark W. Johnson
    • Dale J. DurandQuentin P. HerrMark W. Johnson
    • H03K19195
    • H03K19/1952
    • The level of bias current (12) required by a superconductor integrated circuit (2 & 4) is lowered by separating the circuit into portions having separate ground planes and supplying the bias current to the circuit portion (2) in one ground plane in series (10) with that for the circuit portion (4) in another ground plane. To maintain DC isolation between those circuit portions, SFQ pulses inputted (SFQ IN) move across the separate ground planes through a pair of inductively coupled SQUIDS (3 & 5) that define a DC transformer; and a combiner (7) reconstitutes and outputs the SFQ pulses. To provide inductive coupling the DC transformer includes a primary (25) and isolated secondary (5) winding.
    • 通过将电路分离成具有分离的接地平面的部分并将偏置电流提供给串联的一个接地平面中的电路部分(2)来降低超导体集成电路(2和4)所需的偏置电流(12)的电平( 10)与电路部分(4)在另一个接地平面中的电路部分。 为了保持这些电路部分之间的直流隔离,输入的SFQ脉冲(SFQ IN)通过一对感应耦合的SQUIDS(3和5)在独立的接地层上移动,定义了一个直流变压器; 并且组合器(7)重构并输出SFQ脉冲。 为了提供电感耦合,DC变压器包括初级(25)和隔离次级(5)绕组。
    • 10. 发明授权
    • Battery charging system apparatus and technique
    • 电池充电系统设备及技术
    • US06326770B1
    • 2001-12-04
    • US09655141
    • 2000-09-05
    • Joseph PatinoMark W. Johnson
    • Joseph PatinoMark W. Johnson
    • H02J700
    • H02J7/0072H02J2007/0098
    • A battery charging method (300) determines a current at which to start charging the battery which provides the capability for faster higher current sourcing capability. A start current(Istart)is determined based on the battery's cut off voltage, steady state voltage, and characteristic impedance (314). This start current is then compared and adjusted based on the rated power supply current for the power supply (316, 318) and rated charge current for the battery (320, 322). The adjusted current is then applied to the battery (324) at the beginning of the charge sequence to provide faster higher current sourcing capability.
    • 电池充电方法(300)确定开始对电池充电的电流,其提供更快的较高电流源能力的能力。 基于电池的截止电压,稳态电压和特性阻抗确定启动电流(Istart)(314)。 然后基于电源(316,318)的额定电源电流和电池(320,322)的额定充电电流来比较和调整该启动电流。 然后在电荷序列开始时将调整后的电流施加到电池(324),以提供更快的更高的电流源。