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1. 发明授权

US5986464A Threshold logic circuit with low space requirement 失效
标题翻译：具有低空间要求的阈值逻辑电路
公开(公告)号：US5986464A
公开(公告)日：1999-11-16
申请号：US959257
申请日：1997-10-29
申请人： Andreas Luck , Roland Thewes , Werner Weber
发明人： Andreas Luck , Roland Thewes , Werner Weber
IPC分类号： G06G7/60 , G06F7/52 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H03K19/20 , H03K19/23
CPC分类号： G06F7/53 , G06F2207/4826
摘要： A threshold logic circuit with a low space requirement includes a first and at least one second circuit portion, each of which has an evaluator circuit and at least two branches to be evaluated. A partial sum signal formed in the first circuit portion is jointly used for the at least one second circuit portion and is not formed separately in each case. The main advantage is a low chip area consumption.
摘要翻译：具有低空间要求的阈值逻辑电路包括第一和至少一个第二电路部分，每个第二电路部分具有评估器电路和至少两个待评估的分支。形成在第一电路部分中的部分和信号被共同用于至少一个第二电路部分，并且在每种情况下都不分开形成。主要优点是芯片面积消耗低。

2. 发明授权

US5942912A Devices for the self-adjusting setting of the operating point in amplifier circuits with neuron MOS transistors 失效
标题翻译：用于具有神经元MOS晶体管的放大器电路中的工作点的自调整设置的装置
公开(公告)号：US5942912A
公开(公告)日：1999-08-24
申请号：US900119
申请日：1997-07-25
申请人： Roland Thewes , Werner Weber , Andreas Luck , Doris Schmitt-Landsiedel
发明人： Roland Thewes , Werner Weber , Andreas Luck , Doris Schmitt-Landsiedel
IPC分类号： G06G7/12 , G11C11/54 , H03F1/22 , H03F1/30 , H03F3/16 , H03F3/345 , H03G1/00 , H03K19/23
CPC分类号： H03F3/16 , H03F1/223 , H03F1/301 , H03G1/007
摘要： A defined zero point voltage (V.sub.0), dependent on a settable zero point voltage target value (V.sub.0,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k). This is generally required because, for example, due to a process-caused charging of the floating gates of the neuron MOS transistors, and due to a capacitively coupled-in voltage from the channel region, an undefined zero point displacement of the transmission characteristic curve results. The devices can be used together with the amplifier stages, e.g. in video and audio technology, in sensor technology, in analog computers, in fuzzy circuits and in neural networks.
摘要翻译：依赖于可设定的零点电压目标值（V0，sol1）的定义零点电压（V0）在具有神经元MOS晶体管（T10,1 ... T10，k）的放大器级（1 ... k）中被使能）。这通常是因为，例如，由于神经元MOS晶体管的浮置栅极的处理引起的充电，并且由于来自沟道区的电容耦合电压，传输特性曲线的未定义的零点位移结果。这些器件可以与放大器级一起使用，例如，视频和音频技术，传感器技术，模拟电脑，模糊电路和神经网络。

3. 发明授权

US5939945A Amplifier with neuron MOS transistors 失效
标题翻译：具有神经元MOS晶体管的放大器
公开(公告)号：US5939945A
公开(公告)日：1999-08-17
申请号：US900345
申请日：1997-07-25
申请人： Roland Thewes , Werner Weber , Andreas Luck , Erdmute Wohlrab , Doris Schmitt-Landsiedel
发明人： Roland Thewes , Werner Weber , Andreas Luck , Erdmute Wohlrab , Doris Schmitt-Landsiedel
IPC分类号： H03F1/22 , H03F3/16 , H03G1/00
CPC分类号： H03F1/223 , H03F3/16 , H03G1/007
摘要： Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.
摘要翻译：提供了具有至少一个神经元MOS晶体管的放大器电路，其中耦合栅极连接到放大器输出和至少一个另外的耦合栅极与相应的放大器输入连接。放大器电路即使在大信号操作中也表现出线性传输行为，并且可以使用相对较少的部件来构造。此外，增益容易设定。

4. 发明授权

US6078190A Threshold logic with improved signal-to-noise ratio 失效
标题翻译：具有提高信噪比的阈值逻辑
公开(公告)号：US6078190A
公开(公告)日：2000-06-20
申请号：US117760
申请日：1998-08-06
申请人： Werner Weber , Roland Thewes , Andreas Luck
发明人： Werner Weber , Roland Thewes , Andreas Luck
IPC分类号： G06F7/53 , G06F7/501 , G06F7/52 , G06F7/523 , G06N3/06 , H03K17/30 , H03K19/00 , H03K19/08 , H03K19/20 , H03K19/23 , H03K19/094
CPC分类号： G06F7/53 , H03K19/0027 , H03K19/0813 , G06F2207/4826
摘要： The threshold value logic has a non-inverting circuit path (S) that and an inverting circuit path (S') are connected to at least one comparative weighting subcircuit (BC, BS). The non-inverting circuit path and the inverting circuit path preferably are of identical construction and each contain at least one neuron transistor (NT1, NT1'). The corresponding neuron transistor gates in the non-inverting circuit path and in the inverting circuit path are driven inversely with respect to one another.
摘要翻译： PCT No.PCT / DE97 / 00355 Sec。 371日期1998年8月6日 102（e）1998年8月6日PCT PCT 1997年2月27日提交PCT公布。公开号WO97 / 33372 日期1997年9月12日阈值逻辑具有非反相电路路径（S），并且反相电路路径（S'）连接到至少一个比较加权子电路（BC，BS）。非反相电路路径和反相电路路径优选地具有相同的结构，并且每个包含至少一个神经元晶体管（NT1，NT1'）。非反相电路路径和反相电路路径中相应的神经元晶体管栅极彼此相反地驱动。

5. 发明授权

US6037885A Digital/analog converter using a floating gate MOS neuron transistor with capacitive coupling 失效
标题翻译：数字/模拟转换器采用具有电容耦合的浮栅MOS神经元晶体管
公开(公告)号：US6037885A
公开(公告)日：2000-03-14
申请号：US7252
申请日：1998-01-14
申请人： Doris Schmitt-Landsiedel , Roland Thewes , Doktorand Andreas Luck , Werner Weber
发明人： Doris Schmitt-Landsiedel , Roland Thewes , Doktorand Andreas Luck , Werner Weber
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H03M1/66 , H03M1/74 , H03M1/80 , H03M1/00
CPC分类号： H03M1/802
摘要： A digital/analog converter has a neuron MOS transistor, a maintenance circuit which keeps the drain potential of the neuron MOS transistor constant, and a current source. A linear dynamic range in terms of large signal is possible, so that converters having a larger input word size than, for example, only two bits can be realized in a simple way with low dissipated power. Such converters are of significance particularly for ULSI circuits.
摘要翻译：数字/模拟转换器具有神经元MOS晶体管，保持神经元MOS晶体管的漏极电位恒定的维护电路和电流源。在大信号方面的线性动态范围是可能的，因此具有比例如仅两位更大的输入字大小的转换器可以以低耗散功率以简单的方式实现。这种转换器对于ULSI电路尤其重要。

6. 发明授权

US6160729A Associative memory and method for the operation thereof 有权
标题翻译：关联记忆及其操作方法
公开(公告)号：US6160729A
公开(公告)日：2000-12-12
申请号：US162608
申请日：1998-09-29
申请人： Stefan Jung , Roland Thewes , Werner Weber , Andreas Luck, deceased , by Manfred Luck, heir , by Inge Booken, heir
发明人： Stefan Jung , Roland Thewes , Werner Weber , Andreas Luck, deceased , by Manfred Luck, heir , by Inge Booken, heir
IPC分类号： G11C15/04 , G11C7/00
CPC分类号： G11C15/046
摘要： An associative memory contains cells that are formed of a series circuit of an ordinary PMOS transistor with a PMOS transistor with a floating gate. The ordinary PMOS transistor receives of an input vector and the gate of the second PMOS transistor is connected to a learning input. For the associative access, a second vector can be applied to the drain terminal of the second PMOS transistor and, upon readout, the current flow through the respective series circuit is evaluated column-by-column by current evaluator circuits.
摘要翻译：相关存储器包含由具有带浮置栅极的PMOS晶体管的普通PMOS晶体管的串联电路形成的单元。普通PMOS晶体管接收输入矢量，第二PMOS晶体管的栅极连接到学习输入端。对于关联访问，第二向量可以被施加到第二PMOS晶体管的漏极端子，并且在读出时，通过电流评估器电路逐列地评估通过各个串联电路的电流。

7. 发明授权

US6097661A Pointer circuit with low surface requirement high speed and low power loss 失效
标题翻译：指针电路具有低表面要求高速和低功耗
公开(公告)号：US6097661A
公开(公告)日：2000-08-01
申请号：US161004
申请日：1998-09-25
申请人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu , Ute Kollmer , Andreas Luck, deceased , by Manfred Luck, legal representative , by Inge Booken, legal representative
发明人： Roland Thewes , Doris Schmitt-Landsiedel , Paul-Werner von Basse , Michael Bollu , Ute Kollmer , Andreas Luck, deceased , by Manfred Luck, legal representative , by Inge Booken, legal representative
IPC分类号： G11C19/28 , G11C7/10 , G11C8/04 , G11C7/00
CPC分类号： G11C7/1018 , G11C8/04
摘要： In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.
摘要翻译：在指针电路中，只有一个静态存储器（1）分别分别分配给每个输出（...，An-1，An，An + 1，...），其中每个分别具有一对相互补充的存储器端子（Q，+ E，ovs Q + EE）。两个终端处于彼此不同的两个存储的逻辑状态（“1”，“0”）。每个存储器的存储器端子（Q）与分配给该存储器的输出端连接。存储器由时钟信号控制。这导致有利的表面要求和功率损耗低以及高速度。

8. 发明授权

US07429001B2 Label identification system and coding method suited therefor 失效
标题翻译：标签识别系统及其编码方法
公开(公告)号：US07429001B2
公开(公告)日：2008-09-30
申请号：US10504376
申请日：2003-02-12
申请人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： G06K19/06 , G06K7/08 , H04Q5/22
CPC分类号： G06K7/10336 , G06K7/086 , G06K19/067
摘要： The invention relates to a label identification system comprised of a transmitting-receiving unit and of identification labels on which the identification information is stored in the form of a digital identification information word. The provision of a circuit on the identification label in the form of a circuit arrangement, which is prefabricated using a polymer technique and on which the identification information is subsequently placed by the offset printing of conductor tracks, enables the provision of an identification label involving a minimal consumption of energy during inexpensive mass production. The bulk of the identification information processing is transferred to the transmitting-receiving unit.
摘要翻译：本发明涉及一种标签识别系统，包括发送接收单元和识别标签，识别信息以数字识别信息字的形式存储在其上。使用聚合物技术预制的电路装置形式的识别标签上的电路的提供，并且随后通过导体迹线的胶印印刷识别信息，能够提供涉及在廉价大规模生产中能量消耗最小化。识别信息处理的大部分被传送到发送 - 接收单元。

9. 发明申请

US20070085582A1 ELECTRONIC COMPONENT WITH ID TAGS 有权
标题翻译：具有ID标签的电子组件
公开(公告)号：US20070085582A1
公开(公告)日：2007-04-19
申请号：US10562458
申请日：2004-06-30
申请人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： H03K7/08
CPC分类号： G06K19/0723
摘要： The invention relates to an electronic component that can be operated by means of an alternating voltage. Said component includes at least one input, at least one output and a pair of electronic sub-components with an identical function. The input(s) of the electronic component is/are coupled to a respective input of the electronic sub-components with an identical function and the output(s) of the electronic component is/are coupled to a respective output of said electronic sub-components. In addition, the electronic component is configured in such a way that at least one output only one output signal of the first sub-component of the pair of functionally identical electronic components can be picked up during a first half-wave of an alternating voltage, whereas only one output signal of the second sub-component of the pair of functionally identical electronic can be picked up during the second half-wave of the alternating voltage.
摘要翻译：本发明涉及可以通过交流电压操作的电子部件。所述组件包括具有相同功能的至少一个输入，至少一个输出和一对电子子部件。电子部件的输入端以相同的功能耦合到电子子部件的相应输入端，并且电子部件的输出耦合到所述电子部件的相应输出端，组件。此外，电子部件被配置为使得在交流电压的第一半波期间可以拾取一对功能相同的电子部件中的第一子部件的至少一个输出信号的一个输出信号，而一对功能相同的电子对的第二子分量的一个输出信号可以在交流电压的第二个半波期间被拾取。

10. 发明授权

US06611614B1 Image acquisition apparatus 有权
标题翻译：图像采集装置
公开(公告)号：US06611614B1
公开(公告)日：2003-08-26
申请号：US09597350
申请日：2000-06-19
申请人： Stefan Jung , Roland Thewes , Werner Weber
发明人： Stefan Jung , Roland Thewes , Werner Weber
IPC分类号： G06K900
CPC分类号： G06K9/00067 , G06K9/00973 , G06K9/56 , G06T5/20
摘要： Sensor elements are arranged in a hexagonal grid. A processor element in the form of a primitive automaton is assigned to each of the sensor elements in the grid. The processor elements are set up to perform algorithms which enable lines of a fingerprint to be simplified such that characteristic minutiae of the fingerprint (endings and branchings of the lines) can be extracted. The processor elements are embodied using CMOS/Neuron MOS threshold value logic or using CMOS/NMOS pass transistor logic. The image grid can be read out via read-out circuits as a matrix.
摘要翻译：传感器元件布置在六边形网格中。原始自动机形式的处理器元件被分配给网格中的每个传感器元件。处理器元件被设置为执行能够简化指纹行的算法，使得可以提取指纹的特征细节（结尾和分支）。处理器元件使用CMOS /神经元MOS阈值逻辑或使用CMOS / NMOS传输晶体管逻辑来实现。图像网格可以通过读出电路作为矩阵读出。

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