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1. 发明授权

US08737351B2 Methods and systems for reducing MAC layer handoff latency in wireless networks 有权
标题翻译：减少无线网络中MAC层切换延迟的方法和系统
公开(公告)号：US08737351B2
公开(公告)日：2014-05-27
申请号：US12626738
申请日：2009-11-27
申请人： Andrea Giuseppe Forte , Henning G Schulzrinne , Sangho Shin , Anshuman S Rawat
发明人： Andrea Giuseppe Forte , Henning G Schulzrinne , Sangho Shin , Anshuman S Rawat
IPC分类号： H04W4/00
CPC分类号： H04W36/0016 , H04W36/0083 , H04W36/36
摘要： In accordance with the present invention, computer implemented methods and systems are provided for reducing handoff latency in a wireless network. In response to detecting that a handoff is necessary, the present invention uses a selective scanning algorithm that includes the use of a channel mask and/or a caching algorithm for detecting one or more new access points.
摘要翻译：根据本发明，提供了计算机实现的方法和系统，用于减少无线网络中的切换等待时间。响应于检测到切换是必要的，本发明使用选择性扫描算法，其包括使用信道掩码和/或用于检测一个或多个新接入点的高速缓存算法。

2. 发明申请

US20100135252A1 METHODS AND SYSTEMS FOR REDUCING MAC LAYER HANDOFF LATENCY IN WIRELESS NETWORKS 有权
标题翻译：在无线网络中减少MAC层倒换延迟的方法和系统
公开(公告)号：US20100135252A1
公开(公告)日：2010-06-03
申请号：US12626738
申请日：2009-11-27
申请人： Andrea G. Forte , Henning G. Schulzrinne , Sangho Shin , Anshuman S. Rawat
发明人： Andrea G. Forte , Henning G. Schulzrinne , Sangho Shin , Anshuman S. Rawat
IPC分类号： H04W36/00
CPC分类号： H04W36/0016 , H04W36/0083 , H04W36/36
摘要： In accordance with the present invention, computer implemented methods and systems are provided for reducing handoff latency in a wireless network. In response to detecting that a handoff is necessary, the present invention uses a selective scanning algorithm that includes the use of a channel mask and/or a caching algorithm for detecting one or more new access points.
摘要翻译：根据本发明，提供了计算机实现的方法和系统，用于减少无线网络中的切换等待时间。响应于检测到切换是必要的，本发明使用选择性扫描算法，其包括使用信道掩码和/或用于检测一个或多个新接入点的高速缓存算法。

3. 发明授权

US07636336B2 Methods and systems for reducing MAC layer handoff latency in wireless networks 有权
标题翻译：减少无线网络中MAC层切换延迟的方法和系统
公开(公告)号：US07636336B2
公开(公告)日：2009-12-22
申请号：US11070936
申请日：2005-03-03
申请人： Andrea G. Forte , Henning G. Schulzrinne , Sangho Shin , Anshuman S. Rawat
发明人： Andrea G. Forte , Henning G. Schulzrinne , Sangho Shin , Anshuman S. Rawat
IPC分类号： H04W4/00
CPC分类号： H04W36/0016 , H04W36/0083 , H04W36/36
摘要： In accordance with the present invention, computer implemented methods and systems are provided for reducing handoff latency in a wireless network. In response to detecting that a handoff is necessary, the present invention uses a selective scanning algorithm that includes the use of a channel mask and/or a caching algorithm for detecting one or more new access points.
摘要翻译：根据本发明，提供了计算机实现的方法和系统，用于减少无线网络中的切换等待时间。响应于检测到切换是必要的，本发明使用选择性扫描算法，其包括使用信道掩码和/或用于检测一个或多个新接入点的高速缓存算法。

4. 发明授权

US08270538B2 Apparatus for controlling sensitivity by using digital gating in receiver and receiver with the same 有权
标题翻译：用于通过在接收机和接收机中使用数字门控来控制灵敏度的装置
公开(公告)号：US08270538B2
公开(公告)日：2012-09-18
申请号：US12467627
申请日：2009-05-18
申请人： Sangho Shin , Sang-Hyun Cho , Seok-Oh Yun , Jong-Moon Kim
发明人： Sangho Shin , Sang-Hyun Cho , Seok-Oh Yun , Jong-Moon Kim
IPC分类号： H03D1/24
CPC分类号： H04B1/28 , H04L25/06
摘要： Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC. A receiver includes: a low noise amplifier (LNA) amplifying a received radio (RF) signal while minimizing amplification of noise included in the received RF signal; a mixer down-converting a frequency of an output signal of the LNA to output an intermediate frequency (IF) signal; a frequency synthesizer generating and outputting a frequency signal for the frequency-down conversion of the mixer to the mixer; a bandpass filter passing a necessary band of a channel in an output signal of the mixer; a log amplifier amplifying an output signal of the bandpass filter in log scale and outputting a received signal strength indicator of an output signal of the bandpass filter; a detector comparing an output of the log amplifier with a predetermined binary threshold value, outputting a first binary signal when the output of the log amplifier is less than the predetermined binary threshold value, and outputting a second binary signal when the output of the log amplifier is equal to or greater than the predetermined binary threshold value; a switch serially connected with an output terminal of the detector; and a switch controller comparing the received signal strength indicator of the output signal of the log amplifier with an RSSI threshold, opening the switch when the received signal strength indicator is less than the RSSI threshold, and closing the switch when the received signal strength indicator is equal to or grater than the RSSI threshold.
摘要翻译：公开了一种无线通信系统，更具体地，用于DSRC的接收机和芯片组。接收机包括：放大接收的无线电（RF）信号的低噪声放大器（LNA），同时最小化包含在所接收的RF信号中的噪声的放大; 混频器降频转换LNA的输出信号的频率以输出中频（IF）信号; 频率合成器，生成并输出用于混频器的降频转换的混频器的频率信号; 带通滤波器，在混频器的输出信号中通过通道的必要频带; 对数放大器，以对数标度放大带通滤波器的输出信号，并输出带通滤波器的输出信号的接收信号强度指示符; 将对数放大器的输出与预定的二进制阈值进行比较的检测器，当对数放大器的输出小于预定的二进制阈值时输出第一二进制信号，并且当对数放大器的输出输出时输出第二二进制信号等于或大于预定二进制阈值; 与检测器的输出端子串联连接的开关; 以及开关控制器，将对数放大器的输出信号的接收信号强度指示符与RSSI阈值进行比较，当接收信号强度指示符小于RSSI阈值时打开开关，并且当接收信号强度指示符为等于或大于RSSI阈值。

5. 发明申请

US20080031068A1 DYNAMIC MEMORY REFRESH CONFIGURATIONS AND LEAKAGE CONTROL METHODS 失效
标题翻译：动态记忆刷新配置和泄漏控制方法
公开(公告)号：US20080031068A1
公开(公告)日：2008-02-07
申请号：US11779716
申请日：2007-07-18
申请人： Seung-Moon Yoo , Myung Choi , Sangho Shin , Sang-Kyun Han
发明人： Seung-Moon Yoo , Myung Choi , Sangho Shin , Sang-Kyun Han
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/4094 , G11C29/783 , G11C29/83 , G11C29/832 , G11C2211/4061 , G11C2211/4065 , G11C2211/4067 , G11C2211/4068
摘要： Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.
摘要翻译：描述了用于减少泄漏和提高修复产量的动态随机存取存储器（DRAM）电路和方法。根据本发明，通过在功率控制的单个激活中分组刷新周期，使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗，调制位线在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期，以及它们的组合。在一个方面，字线保险丝将使用模式指示为：未使用，替换，附加刷新以及附加刷新的替换。刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合，用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。

6. 发明申请

US20090316834A1 APPARATUS FOR CONTROLLING SENSITIVITY BY USING DIGITAL GATING IN RECEIVER AND RECEIVER WITH THE SAME 有权
标题翻译：通过在接收机中使用数字增益来控制灵敏度的装置和接收器的接收器
公开(公告)号：US20090316834A1
公开(公告)日：2009-12-24
申请号：US12467627
申请日：2009-05-18
申请人： Sangho Shin , Sang-Hyun Cho , Seok-Oh Yun , Jong-Moon Kim
发明人： Sangho Shin , Sang-Hyun Cho , Seok-Oh Yun , Jong-Moon Kim
IPC分类号： H04L25/06 , H04B1/16 , H03D1/24
CPC分类号： H04B1/28 , H04L25/06
摘要： Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC. A receiver includes: a low noise amplifier (LNA) amplifying a received radio (RF) signal while minimizing amplification of noise included in the received RF signal; a mixer down-converting a frequency of an output signal of the LNA to output an intermediate frequency (IF) signal; a frequency synthesizer generating and outputting a frequency signal for the frequency-down conversion of the mixer to the mixer; a bandpass filter passing a necessary band of a channel in an output signal of the mixer; a log amplifier amplifying an output signal of the bandpass filter in log scale and outputting a received signal strength indicator of an output signal of the bandpass filter; a detector comparing an output of the log amplifier with a predetermined binary threshold value, outputting a first binary signal when the output of the log amplifier is less than the predetermined binary threshold value, and outputting a second binary signal when the output of the log amplifier is equal to or greater than the predetermined binary threshold value; a switch serially connected with an output terminal of the detector; and a switch controller comparing the received signal strength indicator of the output signal of the log amplifier with an RSSI threshold, opening the switch when the received signal strength indicator is less than the RSSI threshold, and closing the switch when the received signal strength indicator is equal to or grater than the RSSI threshold.
摘要翻译：公开了一种无线通信系统，更具体地，用于DSRC的接收机和芯片组。接收机包括：放大接收的无线电（RF）信号的低噪声放大器（LNA），同时最小化包含在所接收的RF信号中的噪声的放大; 混频器降频转换LNA的输出信号的频率以输出中频（IF）信号; 频率合成器，生成并输出用于混频器的降频转换的混频器的频率信号; 带通滤波器，在混频器的输出信号中通过通道的必要频带; 对数放大器，以对数标度放大带通滤波器的输出信号，并输出带通滤波器的输出信号的接收信号强度指示符; 将对数放大器的输出与预定的二进制阈值进行比较的检测器，当对数放大器的输出小于预定的二进制阈值时输出第一二进制信号，并且当对数放大器的输出输出时输出第二二进制信号等于或大于预定二进制阈值; 与检测器的输出端子串联连接的开关; 以及开关控制器，将对数放大器的输出信号的接收信号强度指示符与RSSI阈值进行比较，当接收信号强度指示符小于RSSI阈值时打开开关，并且当接收信号强度指示符为等于或大于RSSI阈值。

7. 发明申请

US20060062183A1 Methods and systems for reducing MAC layer handoff latency in wireless networks 有权
公开(公告)号：US20060062183A1
公开(公告)日：2006-03-23
申请号：US11070936
申请日：2005-03-03
申请人： Andrea Forte , Henning Schulzrinne , Sangho Shin , Anshuman Rawat
发明人： Andrea Forte , Henning Schulzrinne , Sangho Shin , Anshuman Rawat
IPC分类号： H04Q7/00
CPC分类号： H04W36/0016 , H04W36/0083 , H04W36/36
摘要： In accordance with the present invention, computer implemented methods and systems are provided for reducing handoff latency in a wireless network. In response to detecting that a handoff is necessary, the present invention uses a selective scanning algorithm that includes the use of a channel mask and/or a caching algorithm for detecting one or more new access points.

8. 发明授权

US07522464B2 Dynamic memory refresh configurations and leakage control methods 失效
标题翻译：动态内存刷新配置和泄漏控制方法
公开(公告)号：US07522464B2
公开(公告)日：2009-04-21
申请号：US11779716
申请日：2007-07-18
申请人： Seung-Moon Yoo , Myung Chan Choi , Sangho Shin , Sang-Kyun Han
发明人： Seung-Moon Yoo , Myung Chan Choi , Sangho Shin , Sang-Kyun Han
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/4094 , G11C29/783 , G11C29/83 , G11C29/832 , G11C2211/4061 , G11C2211/4065 , G11C2211/4067 , G11C2211/4068
摘要： Dynamic Random Access Memory (DRAM) circuits and methods are described for reducing leakage and increasing repaired yield. These objects are accomplished according to the invention by grouping refresh cycles within a single activation of power control, the use of limiting circuits or fuses to mitigate power losses associated with micro-bridging of bit-lines and word-lines, modulating the bit-line voltage at the end of precharge cycles, configuring refresh control circuits to use redundant word-lines in generating additional refresh cycles for redundant rows of memory cells, and combinations thereof. In one aspect, word-line fuses indicate modes of use as: unused, replacement, additional refresh, and replacement with additional refresh. The refresh control circuit utilizes these modes in combination with the X-address stored in the word-line fuses for controlling the generation of additional refresh cycles toward overcoming insufficient data retention intervals in select memory cell rows.
摘要翻译：描述了用于减少泄漏和提高修复产量的动态随机存取存储器（DRAM）电路和方法。根据本发明，通过在功率控制的单个激活中分组刷新周期，使用限制电路或熔丝来减轻与位线和字线的微桥接相关联的功率损耗，调制位线在预充电周期结束时配置刷新控制电路以使用冗余字线来产生冗余的存储器单元行的附加刷新周期，以及它们的组合。在一个方面，字线保险丝将使用模式指示为：未使用，替换，附加刷新以及附加刷新的替换。刷新控制电路利用这些模式与存储在字线保险丝中的X地址相组合，用于控制产生额外的刷新周期以克服选择存储单元行中的不充足的数据保留间隔。

9. 发明申请

US20050270870A1 Time slot interchange switch with cache 审中-公开
标题翻译：具有缓存的时隙交换开关
公开(公告)号：US20050270870A1
公开(公告)日：2005-12-08
申请号：US11143391
申请日：2005-06-01
申请人： Sangho Shin , Sangho Lee , Kee Park
发明人： Sangho Shin , Sangho Lee , Kee Park
IPC分类号： G11C7/00 , H04Q11/04
CPC分类号： H04Q11/0421 , H04Q2213/13103 , H04Q2213/13216 , H04Q2213/13292 , H04Q2213/13393
摘要： In accordance with the invention, time slot interchange switches (“TSIS”) with a cache memory are described. A time slot interchange switch according to the present invention can include a data memory that receives and stores at least one stream of channel data; a cache memory that receives the at least one stream of channel data; and a microprocessor interface coupled to read data from the cache memory. Accordingly, a method of reading data from a time slot interchange switch to a microprocessor can include writing channel data to a cache memory in addition to a data memory; and providing data from the cache memory in response to requests from a microprocessor interface.
摘要翻译：根据本发明，描述了具有高速缓冲存储器的时隙交换开关（“TSIS”）。根据本发明的时隙交换交换机可以包括接收并存储至少一个信道数据流的数据存储器; 高速缓存存储器，其接收所述至少一个信道数据流; 以及耦合到从高速缓冲存储器读取数据的微处理器接口。因此，从时隙交换开关向微处理器读取数据的方法可以包括除了数据存储器之外还将信道数据写入高速缓存存储器; 以及响应于来自微处理器接口的请求，从高速缓冲存储器提供数据。

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