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1. 发明授权

US07755524B2 Method for performing a digital to analog conversion of a digital signal, and corresponding electronic device 有权
标题翻译：用于执行数字信号的数模转换的方法及相应的电子设备
公开(公告)号：US07755524B2
公开(公告)日：2010-07-13
申请号：US12208966
申请日：2008-09-11
申请人： Andras Pozsgay , Mounir Boulemnakher , Frédéric Paillardet
发明人： Andras Pozsgay , Mounir Boulemnakher , Frédéric Paillardet
IPC分类号： H03M3/00 , H03M1/66 , H04L27/00
CPC分类号： H03M1/745 , H04L27/36
摘要： A method for processing a digital signal includes an elementary processing including a radiofrequency transposition with a radiofrequency transposition signal and a digital to analog conversion of the transposed digital signal for delivering a radiofrequency analog signal. The digital to analog conversion is controlled by a control signal and a power control signal, the control signal having a frequency twice the frequency of the radiofrequency transposition signal. Each transition of the radiofrequency transposition signal occurs between two consecutive pulses of said control signal.
摘要翻译：用于处理数字信号的方法包括基本处理，其包括具有射频转置信号的射频转置和用于传递射频模拟信号的转置数字信号的数模转换。数模转换由控制信号和功率控制信号控制，控制信号的频率是射频转置信号频率的两倍。射频转置信号的每个转换发生在所述控制信号的两个连续脉冲之间。

2. 发明授权

US08165549B2 Method for notch filtering a digital signal, and corresponding electronic device 有权
标题翻译：数字信号陷波滤波方法及相应的电子设备
公开(公告)号：US08165549B2
公开(公告)日：2012-04-24
申请号：US12208921
申请日：2008-09-11
申请人： Andras Pozsgay , Frédéric Paillardet
发明人： Andras Pozsgay , Frédéric Paillardet
IPC分类号： H04B1/06 , H03M1/66 , H04L27/00
CPC分类号： H03H17/025 , H03M3/504
摘要： An electronic device, includes sigma-delta modulation circuit to operate with a clock signal and having output circuitry to deliver a digital data signal. First circuitry delivers a radiofrequency transposition signal. A notch filter includes radiofrequency digital-to-analog conversion blocks, having first input circuitry coupled to the output circuitry. Second input circuitry receives the radiofrequency transposition signal. Second output circuitry delivers a radiofrequency analog signal. Digital delay circuitry is controlled by the clock signal and includes a delay block between the two first input circuits. The frequency of a notch of the notch filter is related to the value of the delay from the delay block. Summation circuitry sums the radiofrequency signals.
摘要翻译：电子设备包括用时钟信号操作并具有输出电路以输送数字数据信号的Σ-Δ调制电路。第一个电路传送一个射频转置信号。陷波滤波器包括射频数模转换块，其具有耦合到输出电路的第一输入电路。第二输入电路接收射频转置信号。第二输出电路提供射频模拟信号。数字延迟电路由时钟信号控制，并且包括两个第一输入电路之间的延迟块。陷波滤波器的陷波的频率与延迟块的延迟值有关。求和电路对射频信号进行求和。

3. 发明授权

US07106808B2 Tuner of the type having zero intermediate frequency and corresponding control process 有权
标题翻译：调谐器具有零中频和相应的控制过程
公开(公告)号：US07106808B2
公开(公告)日：2006-09-12
申请号：US09827306
申请日：2001-04-05
申请人： Pierre Busson , Pierre-Olivier Jouffre , Frédéric Paillardet
发明人： Pierre Busson , Pierre-Olivier Jouffre , Frédéric Paillardet
IPC分类号： H03K9/00
CPC分类号： H03G3/3068 , H03G3/3089
摘要： A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/amplifier stage being fixed.
摘要翻译：调谐器包括模拟块，数字块和连接在它们之间的模拟/数字转换级。模拟模块包括连接到频率转置级上游的第一衰减器/受控增益放大器级。在初始化阶段计算由调谐器接收的整个信号的总平均功率。该总计算功率在数字模块中与对应于模拟模块的预定位置所需的最大功率的第一预定参考值进行比较。调整第一衰减器/放大器级的增益以最小化总计算功率与参考值之间的偏差。在正常操作的相位中，选择所接收的信号中的一个通道，其中第一衰减器/放大器级的增益是固定的。

4. 发明授权

US06522276B2 System of DAC correction for a &Dgr;&Sgr; modulator 有权
标题翻译： DELTASIGMA调制器的DAC校正系统
公开(公告)号：US06522276B2
公开(公告)日：2003-02-18
申请号：US09794409
申请日：2001-06-20
申请人： Eric Andre , Frédéric Paillardet
发明人： Eric Andre , Frédéric Paillardet
IPC分类号： H03M300
CPC分类号： H03M3/388 , G02B13/0095 , G02B17/0808 , G02B17/0812 , G02B17/0852 , G02B17/086 , H03M3/424
摘要： A &Dgr;&Sgr; modulator including a corrector unit for measuring an error due to differences in the operating parameters of individual components of an internal D/A converter, the corrector unit applying a correction of the error measured in this way to a digital signal, the modulator being characterized in that the internal D/A converter includes a number of individual components greater than the number necessary for internal conversion, and in that the corrector unit is suitable for extracting from the internal conversion process, in alternation, on each occasion a different component from the various individual components in order to measure the operating parameter error of the extracted component, while leaving a number of components in action that is sufficient for internal conversion.
摘要翻译：一种DELTASIGMA调制器，包括用于测量由于内部D / A转换器的各个组件的操作参数的差异引起的误差的校正单元，校正单元将以这种方式测量的误差的校正应用于数字信号，调制器为其特征在于，所述内部D / A转换器包括大于内部转换所需数量的多个独立部件，并且所述校正器单元适于从内部转换处理中逐次提取不同的部件，各种单独的组件，以便测量提取的组件的操作参数误差，同时留下足够内部转换的多个组件。

5. 发明授权

US07265636B2 Method of correcting the phase difference between two input signals of a phase-locked loop and associated device 有权
标题翻译：校正锁相环和相关设备的两个输入信号之间的相位差的方法
公开(公告)号：US07265636B2
公开(公告)日：2007-09-04
申请号：US11304382
申请日：2005-12-15
申请人： Sébastien Dedieu , Frédéric Paillardet , Gérald Provins
发明人： Sébastien Dedieu , Frédéric Paillardet , Gérald Provins
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/085 , H03L7/0895
摘要： A method for correcting the phase difference between two input signals of a phase-locked loop may include a charge pump connected to a filter. Prior to the occurrence of the first of the two input signals, a calibration phase may be carried out in which the input of the filter is disconnected from the output of the charge pump, the output voltage from the charge pump is equalized, to within a given error, with the input voltage of the filter, the amplitudes of the opposing currents flowing in the charge pump being equalized. Then, during the two respective occurrences of the two input signals, the input of the filter is reconnected to the output of the charge pump, and two phase-shifted signals that are delayed with respect to the input signals are respectively generated, in response to which the two opposing currents are, respectively and successively, interrupted, before the calibration phase is recommenced.
摘要翻译：用于校正锁相环路的两个输入信号之间的相位差的方法可以包括连接到滤波器的电荷泵。在发生两个输入信号中的第一个信号之前，可以执行校准阶段，其中滤波器的输入与电荷泵的输出断开，来自电荷泵的输出电压相等，给定误差，与滤波器的输入电压相反，在电荷泵中流动的相对电流的幅度相等。然后，在两个输入信号的两个相应出现期间，滤波器的输入被重新连接到电荷泵的输出，并且分别产生相对于输入信号延迟的两个相移信号，响应于在校准阶段重新开始之前，两个相对的电流分别和相继地中断。

6. 发明授权

US06249154B1 Process of controlling a switch of a switched-capacitance device, and corresponding switched-capacitance device 有权
标题翻译：控制开关电容器件的开关和相应的开关电容器件的过程
公开(公告)号：US06249154B1
公开(公告)日：2001-06-19
申请号：US09571392
申请日：2000-05-15
申请人： Pierre-Olivier Jouffre , Isabelle Telliez , Frédéric Paillardet
发明人： Pierre-Olivier Jouffre , Isabelle Telliez , Frédéric Paillardet
IPC分类号： G11C2702
CPC分类号： H03K17/063 , H03K17/165
摘要： With a switch including at least one insulated-gate field-effect transistor, an analog input signal is delivered on the source of the transistor and the transistor is controlled on its gate synchronized with a clock signal to successively turn it on and off. On the conclusion of each half-period of the clock signal during which the transistor is off, a precharging capacitor is precharged at the start of the next half-period and for a predetermined precharge duration, with a predetermined precharge voltage. Then, for the remaining duration of the half-period, the precharged capacitor is connected between the source and the gate of the transistor to turn it on under the action of a gate-source voltage which is almost independent of the level of the input signal. At the end of the half-period, the gate of the transistor and the precharging capacitor are grounded.
摘要翻译：使用包括至少一个绝缘栅场效应晶体管的开关，在晶体管的源极上传送模拟输入信号，并且在其栅极上控制晶体管与时钟信号同步以连续地打开和关闭。在晶体管截止的时钟信号的每个半周期的结论处，预充电电容器在下一个半周期的开始和预定的预充电持续时间内以预定的预充电电压进行预充电。然后，对于半周期的剩余时间，预充电电容器连接在晶体管的源极和栅极之间，以在几乎不依赖于输入信号电平的栅极 - 源极电压的作用下导通。在半周期结束时，晶体管的栅极和预充电电容器接地。

7. 发明授权

US06879643B2 Process and device for controlling the phase shift between four signals mutually in phase quadrature 有权
标题翻译：用于控制相位正交的四个信号之间的相移的处理和装置
公开(公告)号：US06879643B2
公开(公告)日：2005-04-12
申请号：US09859731
申请日：2001-05-17
申请人： Sébastien Dedieu , Frédéric Paillardet , Isabelle Telliez
发明人： Sébastien Dedieu , Frédéric Paillardet , Isabelle Telliez
IPC分类号： H03B27/00 , H03D7/12 , H03H11/22 , H03L7/081 , H03L7/087 , H03K9/00 , H04L27/06 , H04L27/14 , H04L27/22
CPC分类号： H03H11/22 , H03B27/00 , H03D7/125 , H03L7/0812 , H03L7/087
摘要： At least a first base signal and a second base signal are mutually in quadrature and both are capable of mutually exhibiting a quadrature error. These signals are used to formulate two pairs of delayed signals that includes a first delayed signal that is delayed with respect to the first base signal, a second signal delayed in phase opposition with respect to the first delayed signal, a third signal delayed with respect to the second base signal, and a fourth delayed signal in phase opposition with respect to the third delayed signal. The value of each of the delays is continuously adjusted using two differential signals arising from a direct or an indirect cross-mixing of the two pairs of delayed signals to obtain the four delayed signals virtually in quadrature.
摘要翻译：至少第一基本信号和第二基本信号相互正交，并且两者都能够相互呈现正交误差。这些信号用于制定两对延迟信号，这两对延迟信号包括相对于第一基本信号延迟的第一延迟信号，相对于第一延迟信号相位相对延迟的第二信号，相对于第一延迟信号延迟的第三信号第二基本信号和相对于第三延迟信号相位相反的第四延迟信号。使用由两对延迟信号的直接或间接交叉混合产生的两个差分信号来连续地调整每个延迟的值，以获得虚拟地正交的四个延迟信号。

8. 发明授权

US06507305B2 Pipelined analog-to-digital converter with noise shaping 有权
标题翻译：具有噪声整形的流水线模数转换器
公开(公告)号：US06507305B2
公开(公告)日：2003-01-14
申请号：US09855746
申请日：2001-05-16
申请人： Eric Andre , Frédéric Paillardet
发明人： Eric Andre , Frédéric Paillardet
IPC分类号： H03M138
CPC分类号： H03M3/46 , H03M1/164
摘要： An analog-to-digital converter including a first module of the type having a series of processor stages, each of the stages performing two conversions of the signal output by the preceding stage, firstly an analog-to-digital conversion and secondly a digital-to-analog conversion, followed by subtracting the signal obtained from the output signal of the preceding stage to provide the analog output signal of the stage. The first module further assembles together the signals digitized by each stage (S1, . . . , Si) so as to provide an assembled digital signal (SN(nT) which represents the input signal (e(nT) of the converter in digital form. The converter further includes a &Dgr;&Sgr; modulator which digitizes the output signal (b(nT)) from one of the stages, the resulting digitized signal being subtracted from the assembled digital signal (SN(nT)
摘要翻译：一种模数转换器，包括具有一系列处理器级的第一模块，每个级执行前级输出的信号的两个转换，首先是模数转换，其次是数字 - 模拟转换，然后减去从前一级的输出信号获得的信号，以提供级的模拟输出信号。第一模块进一步将由每个级（S1，...，Si）数字化的信号组合在一起，以提供组合的数字信号（SN（nT）），其以数字形式表示转换器的输入信号（e（nT）该转换器还包括一个DELTASIGMA调制器，用于对来自一个级的输出信号（b（nT））进行数字化，从组合的数字信号（SN（nT））中减去得到的数字化信号，

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