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1. 发明申请

US20140351555A1 DIGITAL SIGNAL PROCESSOR AND METHOD FOR ADDRESSING A MEMORY IN A DIGITAL SIGNAL PROCESSOR 有权
标题翻译：数字信号处理器和用于寻址数字信号处理器中的存储器的方法
公开(公告)号：US20140351555A1
公开(公告)日：2014-11-27
申请号：US14364619
申请日：2012-11-28
申请人： Anders Nilsson , Eric Tell , Erik Alfredsson
发明人： Anders Nilsson , Eric Tell , Erik Alfredsson
IPC分类号： G06F9/30 , G06F9/35 , G06F12/06
CPC分类号： G06F9/30036 , G06F9/35 , G06F12/06 , G06F15/8061
摘要： In a digital signal processor comprising at least one vector execution unit and at least a first memory unit a third unit is arranged to provide addressing data in the form of an address vector to be used for addressing the first memory unit said third unit being connectable to the first memory unit through the on-chip network, in such a way that data provided from the third unit can be used to control the reading from and/or the writing to the first memory unit. This enables fast reading from and writing to a memory unit of data in any desired order.
摘要翻译：在包括至少一个向量执行单元和至少第一存储器单元的数字信号处理器中，第三单元被布置为提供地址向量形式的寻址数据，以用于寻址第一存储器单元，所述第三单元可连接到通过片上网络的第一存储器单元，使得从第三单元提供的数据可以用于控制对第一存储器单元的读取和/或写入。这使得能够以任何所需的顺序快速读取和写入数据的存储单元。

2. 发明授权

US09557996B2 Digital signal processor and method for addressing a memory in a digital signal processor 有权
标题翻译：用于寻址数字信号处理器中的存储器的数字信号处理器和方法
公开(公告)号：US09557996B2
公开(公告)日：2017-01-31
申请号：US14364619
申请日：2012-11-28
申请人： Anders Nilsson , Eric Tell , Erik Alfredsson
发明人： Anders Nilsson , Eric Tell , Erik Alfredsson
IPC分类号： G06F3/00 , G06F12/02 , G06F13/00 , G06F9/30 , G06F15/80 , G06F9/35 , G06F12/06
CPC分类号： G06F9/30036 , G06F9/35 , G06F12/06 , G06F15/8061
摘要： In a digital signal processor comprising at least one vector execution unit and at least a first memory unit a third unit is arranged to provide addressing data in the form of an address vector to be used for addressing the first memory unit, said third unit being connectable to the first memory unit through the on-chip network, in such a way that data provided from the third unit can be used to control the reading from and/or the writing to the first memory unit. This enables fast reading from and writing to a memory unit of data in any desired order.
摘要翻译：在包括至少一个向量执行单元和至少第一存储器单元的数字信号处理器中，第三单元被布置成以要用于寻址第一存储器单元的地址向量的形式提供寻址数据，所述第三单元可连接通过片上网络向第一存储器单元提供从第三单元提供的数据可以用于控制对第一存储器单元的读取和/或写入的方式。这使得能够以任何所需的顺序快速读取和写入数据的存储单元。

3. 发明申请

US20070198815A1 Programmable digital signal processor having a clustered SIMD microarchitecture including a complex short multiplier and an independent vector load unit 审中-公开
标题翻译：具有集成SIMD微架构的可编程数字信号处理器，其包括复数短乘法器和独立向量负载单元
公开(公告)号：US20070198815A1
公开(公告)日：2007-08-23
申请号：US11201841
申请日：2005-08-11
申请人： Dake Liu , Anders Nilsson , Eric Tell
发明人： Dake Liu , Anders Nilsson , Eric Tell
IPC分类号： G06F9/44
CPC分类号： G06F9/3885 , G06F7/4812 , G06F7/5443 , G06F7/57 , G06F9/3001 , G06F9/325 , G06F9/342 , G06F9/3822 , G06F9/3853 , G06F9/3891 , G06F15/8092
摘要： A programmable digital signal processor with a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core, and a complex computing unit. Each of the accelerator units may perform one or more dedicated functions. The processor core includes an integer execution unit that may execute integer instructions. The complex computing unit may include a complex arithmetic logic unit execution pipeline that may include one or more datapaths configured to execute complex vector instructions, and a vector load unit. In addition, each datapath may include a complex short multiplier accumulator unit that may be configured to multiply a complex data value by values in the set of numbers including {0, +/−1}+{0, +/−i}. The vector load unit may cause the complex vector instructions to be fetched each clock cycle for use by any datapath in the complex arithmetic logic unit execution pipeline.
摘要翻译：具有集群SIMD微体系结构的可编程数字信号处理器包括多个加速器单元，处理器核心和复合计算单元。每个加速器单元可以执行一个或多个专用功能。处理器核心包括可执行整数指令的整数执行单元。复合计算单元可以包括复杂算术逻辑单元执行流水线，其可以包括被配置为执行复向量指令的一个或多个数据路径和向量加载单元。另外，每个数据路径可以包括复数的短乘法器累加器单元，其可以被配置为将复数数据值乘以包括{0，+/- 1} + {0，+/- i}的数字集合中的值。矢量加载单元可能会导致每个时钟周期提取复矢量指令，以供复杂算术逻辑单元执行流水线中的任何数据路径使用。

4. 发明申请

US20140372728A1 VECTOR EXECUTION UNIT FOR DIGITAL SIGNAL PROCESSOR 审中-公开
标题翻译：用于数字信号处理器的矢量执行单元
公开(公告)号：US20140372728A1
公开(公告)日：2014-12-18
申请号：US14364651
申请日：2012-11-28
申请人： Anders Nilsson , Eric Tell
发明人： Anders Nilsson , Eric Tell
IPC分类号： G06F9/30 , G06F15/78
CPC分类号： G06F9/30145 , G06F9/30021 , G06F9/30094 , G06F9/3887 , G06F15/78 , G06F15/8084
摘要： A vector execution unit for use in a digital signal processor enables a new set of instructions. The unit comprises a first input port for receiving at least a first input data vector, an instruction decoder, a vector output port, and least one data-path. The instruction decoding unit is arranged to control the data-path to perform a comparison related to the first input data vector, and the processor comprises an integer port arranged to output the result of the comparison in the form of a decision vector to a memory unit or a functional unit in the digital signal processor. Alternatively or in addition, the integer port is also arranged to receive a decision vector of integer data, and the instruction decoding unit is arranged to control the data-path to process the first input data in dependence of the value of the integer data.
摘要翻译：用于数字信号处理器的矢量执行单元能够实现新的一组指令。该单元包括用于接收至少第一输入数据向量，指令解码器，向量输出端口和至少一个数据路径的第一输入端口。所述指令解码单元被配置为控制所述数据路径以执行与所述第一输入数据向量相关的比较，并且所述处理器包括整数端口，所述整数端口被布置为将所述比较结果以决策向量的形式输出到存储器单元或数字信号处理器中的功能单元。或者或另外，整数端口还被布置为接收整数数据的判决向量，并且指令解码单元被布置为根据整数数据的值来控制数据路径来处理第一输入数据。

5. 发明授权

US08874968B1 Method and system for testing a processor designed by a configurator 有权
标题翻译：用于测试由配置器设计的处理器的方法和系统
公开(公告)号：US08874968B1
公开(公告)日：2014-10-28
申请号：US13458918
申请日：2012-04-27
申请人： Anders Nilsson , Eric Tell , Olof Kraigher
发明人： Anders Nilsson , Eric Tell , Olof Kraigher
IPC分类号： G06F11/00
CPC分类号： G06F11/3672
摘要： The present invention provides a system and method that includes a library module including a plurality of programmable components and at least one corresponding test case for each programmable component. The system also includes the configurator module coupled to the library module and accessing at least one of the plurality of programmable components and the at least one corresponding test case. The configurator module further outputs a code describing a processor for running a software-defined digital signal processor and includes the accessed programmable component and a plurality of interconnections linking the accessed programmable component. The system further includes a test case generator coupled to the configurator to output a test suite including the at least one corresponding test case for each accessed programmable component and a plurality of interconnect tests to test the plurality of interconnections linking the accessed programmable component.
摘要翻译：本发明提供一种系统和方法，该系统和方法包括一个库模块，该库模块包括多个可编程组件和至少一个对应的每个可编程组件的测试用例。该系统还包括耦合到库模块的配置器模块并且访问多个可编程组件和至少一个相应测试用例中的至少一个。配置器模块还输出描述用于运行软件定义的数字信号处理器的处理器的代码，并且包括所访问的可编程组件和链接所访问的可编程组件的多个互连。所述系统还包括耦合到所述配置器的测试用例发生器，以输出测试套件，所述测试套件包括用于每个可访问的可编程组件的所述至少一个相应的测试用例以及用于测试所述多个互连链接所访问的可编程组件的多个互连测试。

6. 发明申请

US20060271764A1 Programmable digital signal processor including a clustered SIMD microarchitecture configured to execute complex vector instructions 有权
标题翻译：可编程数字信号处理器包括配置成执行复矢量指令的集群SIMD微体系结构
公开(公告)号：US20060271764A1
公开(公告)日：2006-11-30
申请号：US11201842
申请日：2005-08-11
申请人： Anders Nilsson , Eric Tell , Dake Liu
发明人： Anders Nilsson , Eric Tell , Dake Liu
IPC分类号： G06F15/00
CPC分类号： G06F9/30079 , G06F9/30014 , G06F9/30036 , G06F9/3851 , G06F9/3885 , G06F9/3891 , G06F15/7842 , G06F15/8092
摘要： A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.
摘要翻译：包括集群SIMD微体系结构的可编程数字信号处理器包括多个加速器单元，处理器核和复合计算单元。每个加速器单元可以被配置为执行一个或多个专用功能。处理器核心包括可被配置为执行整数指令的整数执行单元。复合计算单元可以被配置为执行复向量指令。复合计算单元可以包括第一和第二群集执行流水线。第一群集执行流水线可以包括被配置为执行第一复合向量指令的一个或多个复杂算术逻辑单元数据路径。第二群集执行流水线可以包括被配置为执行第二复合向量指令的一个或多个复数乘法器累加器数据路径。

7. 发明申请

US20140344549A1 DIGITAL SIGNAL PROCESSOR AND BASEBAND COMMUNICATION DEVICE 审中-公开
标题翻译：数字信号处理器和基带通信设备
公开(公告)号：US20140344549A1
公开(公告)日：2014-11-20
申请号：US14364629
申请日：2012-11-28
申请人： Anders Nilsson , Eric Tell
发明人： Anders Nilsson , Eric Tell
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3836 , G06F9/3851 , G06F9/3887 , G06F15/8053
摘要： The invention relates to a digital signal processor comprising a processor core, an integer execution unit and a number of vector execution units, said digital signal processor comprising a program memory arranged to hold instructions for the execution units and issue logic for issuing instructions. The digital signal processor comprises an issue control unit for selecting at least two execution units that are to receive and execute the same instruction at the same time, and logic for sending the instruction to said at least two execution units.
摘要翻译：本发明涉及包括处理器核心，整数执行单元和多个向量执行单元的数字信号处理器，所述数字信号处理器包括程序存储器，该程序存储器被设置为保存用于执行单元的指令并发出用于发出指令的逻辑。数字信号处理器包括一个问题控制单元，用于选择同时接收和执行相同指令的至少两个执行单元，以及将指令发送到所述至少两个执行单元的逻辑。

8. 发明申请

US20060271765A1 Digital signal processor including a programmable network 有权
标题翻译：数字信号处理器包括可编程网络
公开(公告)号：US20060271765A1
公开(公告)日：2006-11-30
申请号：US11135964
申请日：2005-05-24
申请人： Eric Tell , Anders Nilsson , Dake Liu
发明人： Eric Tell , Anders Nilsson , Dake Liu
IPC分类号： G06F15/00
CPC分类号： G06F15/7857 , G06F9/30036 , G06F9/30079 , G06F9/3851 , G06F9/3885 , G06F9/3891 , H04B1/0003 , Y02D10/13
摘要： A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.
摘要翻译：可编程数字信号处理器包括多个存储器单元，多个加速器单元和处理器核。数字信号处理器还包括可配置为选择性地提供存储器单元，加速器单元和处理器核之间的连接的可编程网络。每个加速器单元可以被配置为执行一个或多个专用功能。处理器核心可以包括可被配置为执行与数据路径流控制相关联的指令的执行单元。可编程网络可以被配置为响应于特定指令的执行选择性地提供连接。

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