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1. 发明授权

US06759921B1 Characteristic impedance equalizer and an integrated circuit package employing the same 有权
标题翻译：特征阻抗均衡器和采用该阻抗均衡器的集成电路封装
公开(公告)号：US06759921B1
公开(公告)日：2004-07-06
申请号：US09932716
申请日：2001-08-17
申请人： Anand Govind , Yogendra Ranade
发明人： Anand Govind , Yogendra Ranade
IPC分类号： H03H738
CPC分类号： H05K1/025 , H01L23/36 , H01L23/49816 , H01L23/66 , H01L2224/16 , H01L2924/00014 , H01L2924/15173 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K2201/09727 , H01L2224/0401
摘要： The present invention provides a characteristic impedance equalizer and method of manufacture thereof for use with an integrated circuit package having first and second signal transmission zones. In one embodiment, the characteristic impedancs equalizer includes a first conductor having a first width and providing a characteristic impedance within the first signal transmission zone. The characteristic impedance equalizer also includes a second conductor, coupled to the first conductor, having a second width and providing substantially the same characteristic impedance within the second signal transmission zone.
摘要翻译：本发明提供一种特征阻抗均衡器及其制造方法，该集成电路封装具有第一和第二信号传输区域。在一个实施例中，特征阻抗均衡器包括具有第一宽度并在第一信号传输区内提供特性阻抗的第一导体。特征阻抗均衡器还包括耦合到第一导体的第二导体，具有第二宽度并且在第二信号传输区域内提供基本上相同的特性阻抗。

2. 发明授权

US06825066B2 Stiffener design 有权
标题翻译：加固设计
公开(公告)号：US06825066B2
公开(公告)日：2004-11-30
申请号：US10308310
申请日：2002-12-03
申请人： Yogendra Ranade , Anand Govind , Kumar Nagarajan , Farshad Ghahghahi , Aritharan Thurairajaratnam
发明人： Yogendra Ranade , Anand Govind , Kumar Nagarajan , Farshad Ghahghahi , Aritharan Thurairajaratnam
IPC分类号： H01L2144
CPC分类号： H01L23/04 , H01L23/50 , H01L25/165 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses. Because the major interior apertures does not need to be large enough to fit both the monolithic integrated circuit and the secondary circuit structure, there is more stiffener material available to provide structural support than there would be if the major interior aperture was large enough to fit both the monolithic integrated circuit and the secondary circuit structure.
摘要翻译：用于加强封装集成电路的加强件。加强件包括刚性平面元件，其具有用于结合到封装基板的第一表面。刚性平面元件形成用于在集成电路的所有侧面上接收和围绕集成电路的主要内部孔。刚性平面元件还形成次要内孔，用于在次级电路结构的至少三侧上接收和围绕次级电路结构。以这种方式，加强件提供对集成电路封装的结构支撑，其降低并优选地消除了衬底封装在其加热并经受其它应力时的扭曲和翘曲。因为主要内部孔径不需要足够大以适合单片集成电路和次级电路结构，所以有更多的加强材料可用于提供结构支撑，如果主要内部孔径足够大以适合于两者单片集成电路和二次电路结构。

3. 发明申请

US20060131283A1 Method and apparatus for forming angled vias in an integrated circuit package substrate 审中-公开
标题翻译：用于在集成电路封装衬底中形成倾斜通孔的方法和装置
公开(公告)号：US20060131283A1
公开(公告)日：2006-06-22
申请号：US11016440
申请日：2004-12-17
申请人： Jeffrey Hall , Yogendra Ranade , Sarathy Rajagopalan
发明人： Jeffrey Hall , Yogendra Ranade , Sarathy Rajagopalan
IPC分类号： B23K26/38
CPC分类号： H01L21/486 , H01L23/49816 , H01L23/49827 , H01L2224/48227 , H01L2924/15174 , H01L2924/15311 , H05K1/115 , H05K3/0032 , H05K3/0047 , H05K3/42 , H05K2201/09836 , Y10T408/86
摘要： A method and apparatus for making angled vias in an integrated circuit package substrate includes providing an integrated circuit package substrate having an upper surface and a lower surface. A first position is selected for a first via opening on the upper surface of the package substrate, and a second position is selected for a second via opening on the lower surface of the package substrate. A selected non-vertical angle is determined for forming an angled via through the first position and the second position. The angled via is formed through the first position and the second position at the selected non-vertical angle.
摘要翻译：一种用于在集成电路封装衬底中形成倾斜通孔的方法和装置包括提供具有上表面和下表面的集成电路封装衬底。对于封装基板的上表面上的第一通孔，选择第一位置，并且在封装基板的下表面上选择用于第二通孔的第二位置。确定所选择的非垂直角以形成通过第一位置和第二位置的成角度的通孔。成角度的通孔以选定的非垂直角通过第一位置和第二位置形成。

4. 发明申请

US20060160269A1 Method and apparatus for avoiding dicing chip-outs in integrated circuit die 有权
标题翻译：用于避免集成电路芯片中切割芯片的方法和装置
公开(公告)号：US20060160269A1
公开(公告)日：2006-07-20
申请号：US11132751
申请日：2005-05-18
申请人： Parthasarathy Rajagopalan , Zafer Kutlu , Emery Sugasawara , Charles Vonderach , Dilip Vijay , Yogendra Ranade , Jeff Hall , Dwight Manning
发明人： Parthasarathy Rajagopalan , Zafer Kutlu , Emery Sugasawara , Charles Vonderach , Dilip Vijay , Yogendra Ranade , Jeff Hall , Dwight Manning
IPC分类号： H01L21/50 , H01L21/78 , H01L23/02
CPC分类号： H01L21/78 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
摘要翻译：一种用于避免集成电路管芯中的切割切屑的方法和装置包括：（a）提供用于在其上形成多个集成电路管芯的晶片; （b）在晶片上形成多个集成电路管芯; 以及（c）在晶片上的集成电路裸片之间形成锯路，以在集成电路管芯被切割锯分离时减轻晶片中的切割应力。

5. 发明申请

US20130203483A1 VIRTUAL CURRENCY BASED ONLINE SOCIAL WAGERING SYSTEM AND METHOD 审中-公开
标题翻译：基于虚拟货币的在线社会融合系统与方法
公开(公告)号：US20130203483A1
公开(公告)日：2013-08-08
申请号：US13757788
申请日：2013-02-02
申请人： Ashish Joshi , Yogendra Ranade
发明人： Ashish Joshi , Yogendra Ranade
IPC分类号： G06F17/00
CPC分类号： G06F17/00 , G06Q20/0655 , G06Q50/01 , G06Q50/34 , G07F17/3244 , G07F17/3288
摘要： A virtual currency based online social wagering system and method, based on at least one wagering networks server. The system can handle wagers initiated by multiple users using commonly available computerized devices such as Smartphones. The system avoids legal problems through the use of virtual currency rather than money (which makes the interactions wager-like events, rather than actual wagers), and facilitates interactions between friends by drawing upon social networks for much of the interactions. The system is also designed to make friendly social interactions such as banter, “trash talk”, or “swagger” a key part of the wagering experience. Various internal controls insure that the virtual funds are managed correctly.
摘要翻译：基于虚拟货币的在线社交投注系统和方法，基于至少一个投注网络服务器。系统可以处理由多个用户使用常用的计算机化设备（如智能手机）发起的投注。该系统通过使用虚拟货币而不是货币来避免法律问题（这使得互动投注类似的事件而不是实际的赌注），并通过利用社交网络来促进朋友之间的交互，从而进行大部分的交互。该系统的目的还是将友好的社交互动，如“捣蛋谈话”，或“赃物”作为投注经验的关键部分。各种内部控制确保虚拟资金得到正确管理。

6. 发明申请

US20060071327A1 Construction to improve thermal performance and reduce die backside warpage 有权
公开(公告)号：US20060071327A1
公开(公告)日：2006-04-06
申请号：US10954940
申请日：2004-09-30
申请人： Rajagopalan Parthasarathy , Kishore Desai , Yogendra Ranade
发明人： Rajagopalan Parthasarathy , Kishore Desai , Yogendra Ranade
IPC分类号： H01L23/34
CPC分类号： H01L23/433 , H01L23/42 , H01L2224/16 , H01L2224/32014 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/3511 , H01L2224/0401
摘要： A semiconductor package construction aimed at improving thermal performance. A heatspreader is provided having a metal alloy preform attached to it already. Then, a few dots of conductive epoxy are dispensed around the die. The heatspreader with the preformed metal alloy is pressed on the adhesive and then the part is cured. By coupling the die to the heatspreader with conductive epoxy, the die is constrained from warping. By removing the necessity of coating the die, the cost of fabrication is reduced. There is only a very marginal cost increase in the back end for dispensing the dots. For this, the process and equipment already exists in the backend. By reducing die backside warpage due, the die remains in good contact with the heatspreader, thus improving thermal performance.

7. 发明授权

US07354790B2 Method and apparatus for avoiding dicing chip-outs in integrated circuit die 有权
标题翻译：用于避免集成电路芯片中切割芯片的方法和装置
公开(公告)号：US07354790B2
公开(公告)日：2008-04-08
申请号：US11132751
申请日：2005-05-18
申请人： Parthasarathy Rajagopalan , Zafer Kutlu , Emery O. Sugasawara , Charles E. Vonderach , Dilip P. Vijay , Yogendra Ranade , Jeff Hall , Dwight Manning
发明人： Parthasarathy Rajagopalan , Zafer Kutlu , Emery O. Sugasawara , Charles E. Vonderach , Dilip P. Vijay , Yogendra Ranade , Jeff Hall , Dwight Manning
IPC分类号： H01L21/66
CPC分类号： H01L21/78 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
摘要翻译：一种用于避免集成电路管芯中的切割切屑的方法和装置包括：（a）提供用于在其上形成多个集成电路管芯的晶片; （b）在晶片上形成多个集成电路管芯; 以及（c）在晶片上的集成电路裸片之间形成锯路，以在集成电路管芯被切割锯分离时减轻晶片中的切割应力。

8. 发明申请

US20070013068A1 Integrated circuit package and method with an electrical component embedded in a substrate via 审中-公开
标题翻译：集成电路封装和方法，其中嵌入在基板通孔中的电气部件
公开(公告)号：US20070013068A1
公开(公告)日：2007-01-18
申请号：US11156151
申请日：2005-06-17
申请人： Yogendra Ranade , Parthasarathy Rajagopalan , Jeff Hall
发明人： Yogendra Ranade , Parthasarathy Rajagopalan , Jeff Hall
IPC分类号： H01L23/48
CPC分类号： H01L23/49822 , H01L21/4857 , H01L21/486 , H01L23/49827 , H01L23/49833 , H01L2224/16 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H05K1/184 , H05K3/321 , H05K3/4046 , H05K3/4623 , H05K2201/09536 , H05K2201/096 , H05K2201/10636 , Y02P70/611
摘要： An integrated circuit package and method exploit the volume enclosed by the package substrate vias. In one embodiment, an integrated circuit package includes a first substrate having electrically conductive layers formed on substantially parallel surfaces of the first substrate, a second substrate having electrically conductive layers formed on substantially parallel surfaces of the second substrate, a substrate via formed through the first substrate and the second substrate to form an electrical connection between at least two electrically conductive layers of the first substrate and between at least two electrically conductive layers of the second substrate, an electrical component having a first end and a second end inserted into the substrate via so that the first end extends at least partially inside the first substrate and the second end extends at least partially inside the second substrate, and an electrically insulating layer formed between the first substrate and the second substrate.
摘要翻译：集成电路封装和方法利用封装衬底通孔所包围的体积。在一个实施例中，集成电路封装包括具有形成在第一衬底的基本平行的表面上的导电层的第一衬底，具有形成在第二衬底的基本平行的表面上的导电层的第二衬底，衬底和第二衬底，以在第一衬底的至少两个导电层之间和第二衬底的至少两个导电层之间形成电连接，电子部件具有插入到衬底中的第一端和第二端使得第一端部至少部分地在第一基板内部延伸，并且第二端部至少部分地延伸到第二基板内部，以及形成在第一基板和第二基板之间的电绝缘层。

9. 发明授权

US07145232B2 Construction to improve thermal performance and reduce die backside warpage 有权
标题翻译：结构提高散热性能，减少模具背面翘曲
公开(公告)号：US07145232B2
公开(公告)日：2006-12-05
申请号：US10954940
申请日：2004-09-30
申请人： Rajagopalan Parthasarathy , Kishore Desai , Yogendra Ranade
发明人： Rajagopalan Parthasarathy , Kishore Desai , Yogendra Ranade
IPC分类号： H01L23/34
CPC分类号： H01L23/433 , H01L23/42 , H01L2224/16 , H01L2224/32014 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/3511 , H01L2224/0401
摘要： A semiconductor package construction aimed at improving thermal performance. A heatspreader is provided having a metal alloy preform attached to it already. Then, a few dots of conductive epoxy are dispensed around the die. The heatspreader with the preformed metal alloy is pressed on the adhesive and then the part is cured. By coupling the die to the heatspreader with conductive epoxy, the die is constrained from warping. By removing the necessity of coating the die, the cost of fabrication is reduced. There is only a very marginal cost increase in the back end for dispensing the dots. For this, the process and equipment already exists in the backend. By reducing die backside warpage due, the die remains in good contact with the heatspreader, thus improving thermal performance.
摘要翻译：旨在提高热性能的半导体封装结构。提供了具有附着在其上的金属合金预制件的散热器。然后，在模具周围分配几点导电环氧树脂。将具有预制金属合金的散热器压在粘合剂上，然后将部件固化。通过将模具与导电环氧树脂耦合到散热器，模具受到翘曲限制。通过去除涂覆模具的必要性，制造成本降低。在后端分配点，只有非常边际的成本增加。为此，后台已经存在过程和设备。通过减少模具背面翘曲，芯片保持与散热器的良好接触，从而提高热性能。

10. 发明申请

US20060043603A1 Low temperature PB-free processing for semiconductor devices 审中-公开
标题翻译：半导体器件的低温无铅处理
公开(公告)号：US20060043603A1
公开(公告)日：2006-03-02
申请号：US10932174
申请日：2004-08-31
申请人： Yogendra Ranade , Rajagopalan Parthasarathy , Jeffrey Hall
发明人： Yogendra Ranade , Rajagopalan Parthasarathy , Jeffrey Hall
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L24/81 , H01L23/49816 , H01L23/49833 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H05K3/3436 , H05K3/3463 , H05K2201/10378 , H05K2201/10992 , Y02P70/613 , H01L2224/0401
摘要： Techniques for utilizing a bonding agent that allows a solder reflow process to occur at a lower reflow temperature. One area of use includes semiconductor device manufacturing processes. The bonding agent is placed between a solder ball and a contact surface. The bonding agent has a melting temperature that is lower than that of the solder ball. Reflow is then performed at a relative low temperature that is high enough for reflowing the bonding agent, yet at the same time, lower than what would be necessary to reflow the solder material. Since, the electrical system is not subjected to the high temperatures necessary for reflowing the solder material, the electronic system experiences less high-temperature related damage.
摘要翻译：用于利用允许焊料回流工艺在较低回流温度下发生的粘结剂的技术。一个使用领域包括半导体器件制造工艺。粘结剂置于焊球和接触表面之间。粘合剂的熔融温度低于焊球的熔融温度。然后在足够高的回流焊接剂的相对低温下进行回流，同时低于回流焊料材料所需的回流。由于电气系统没有经受回流焊料所需的高温，所以电子系统的高温相关损害较少。

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