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1. 发明申请

US20050164468A1 Selective silicon-on-insulator isolation structure and method 有权
公开(公告)号：US20050164468A1
公开(公告)日：2005-07-28
申请号：US11082993
申请日：2005-03-17
申请人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.

2. 发明申请

US20080029818A1 SELECTIVE SILICON-ON-INSULATOR ISOLATION STRUCTURE AND METHOD 有权
标题翻译：选择性绝缘子绝缘体隔离结构和方法
公开(公告)号：US20080029818A1
公开(公告)日：2008-02-07
申请号：US11871249
申请日：2007-10-12
申请人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L27/12
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

3. 发明授权

US07326983B2 Selective silicon-on-insulator isolation structure and method 有权
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US07326983B2
公开(公告)日：2008-02-05
申请号：US11082993
申请日：2005-03-17
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L27/108
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

4. 发明授权

US07923786B2 Selective silicon-on-insulator isolation structure and method 有权
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US07923786B2
公开(公告)日：2011-04-12
申请号：US11871249
申请日：2007-10-12
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/70
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

5. 发明授权

US06936522B2 Selective silicon-on-insulator isolation structure and method 失效
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US06936522B2
公开(公告)日：2005-08-30
申请号：US10604102
申请日：2003-06-26
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

6. 发明申请

US20070121370A1 SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS 有权
标题翻译：用于改进操作标准的SRAM电压控制
公开(公告)号：US20070121370A1
公开(公告)日：2007-05-31
申请号：US11164556
申请日：2005-11-29
申请人： Wayne Ellis , Randy Mann , David Wager , Robert Wong
发明人： Wayne Ellis , Randy Mann , David Wager , Robert Wong
IPC分类号： G11C11/00
CPC分类号： G11C5/14 , G11C11/413
摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.
摘要翻译：提供了包括以阵列布置的多个SRAM单元的静态随机存取存储器（“SRAM”）。阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的多个电压控制。多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于所选列列的多个SRAM单元的电源输入的电压的功能 SRAM。选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。

7. 发明申请

US20050073874A1 Method to improve cache capacity of SOI and bulk 有权
公开(公告)号：US20050073874A1
公开(公告)日：2005-04-07
申请号：US10678508
申请日：2003-10-03
申请人： Yuen Chan , Louis Hsu , Rajiv Joshi , Robert Wong
发明人： Yuen Chan , Louis Hsu , Rajiv Joshi , Robert Wong
IPC分类号： G11C11/41 , G11C11/00 , G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412
摘要： Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

8. 发明授权

US4436848A Aqueous co-emulsions of epoxy resin and mineral oil 失效
标题翻译：环氧树脂和矿物油的水性共乳液
公开(公告)号：US4436848A
公开(公告)日：1984-03-13
申请号：US484131
申请日：1983-04-12
申请人： Richard M. Haines , Robert Wong , Elisabeth J. Berger
发明人： Richard M. Haines , Robert Wong , Elisabeth J. Berger
IPC分类号： C08J3/03 , B32B17/08 , B32B17/10 , C08L1/28 , C08L63/02
CPC分类号： C08J3/03 , C08J2363/00 , Y10T428/2938
摘要： An aqueous emulsion of epoxy resin or epoxy resin solution and mineral oil can be formed using a low level of predominantly non-ionic surfactant and an anti-static agent.
摘要翻译：可以使用低水平的主要是非离子表面活性剂和抗静电剂形成环氧树脂或环氧树脂溶液和矿物油的水性乳液。

9. 发明申请

US20160048804A1 SYSTEMS AND METHODS FOR TRANSPORTATION SERVICES FOR PACKAGE DELIVERY 审中-公开
标题翻译：运输服务的系统和方法
公开(公告)号：US20160048804A1
公开(公告)日：2016-02-18
申请号：US14573401
申请日：2014-12-17
申请人： Sunil Paul , Jahan Khanna , Robert Wong , Robert Moran , Thomas Gellatly
发明人： Sunil Paul , Jahan Khanna , Robert Wong , Robert Moran , Thomas Gellatly
IPC分类号： G06Q10/08
CPC分类号： G06Q10/08355
摘要： Systems, methods and a computer-readable medium provide for package delivery by transportation services that transport one or more passenger to desired locations. In one or more embodiments, a transportation server identifies a package delivery location for a package. The transportation server determines a route characteristic based at least on the package delivery location. The transportation server sends the route characteristic to a transportation service for transporting at least one passenger to a passenger drop-off location.
摘要翻译：系统，方法和计算机可读介质通过将一个或多个乘客运送到所需位置的运输服务来提供包装递送。在一个或多个实施例中，运输服务器识别包裹的包裹递送位置。运输服务器至少基于包裹递送位置来确定路线特性。运输服务器将路线特征发送到运输服务，以运送至少一个乘客到乘客下车位置。

10. 发明申请

US20070164365A1 SINGLE STRESS LINER FOR MIGRATION STABILITY AND SPEED 审中-公开
标题翻译：用于移动稳定性和速度的单应力衬管
公开(公告)号：US20070164365A1
公开(公告)日：2007-07-19
申请号：US11306943
申请日：2006-01-17
申请人： Joseph Chan , Robert Wong
发明人： Joseph Chan , Robert Wong
IPC分类号： H01L29/94
CPC分类号： H01L27/1104 , H01L29/7843
摘要： A single stress liner is applied over different type semiconductor devices. The single stress liner avoids the problems of a dual/hybrid stress liner scheme by eliminating the meeting area. The single stress liner may be tensile or compressive. In one embodiment, the semiconductor device includes a static random access memory (SRAM) cell having numerous NFETs and PFETs. In this case, a compressive liner is placed over the SRAM cell, which is normally not ideal for the NFETs therein, but is desirable for the SRAM cell because continued miniaturization of the SRAMs typically requires slowing of the NFETs for the SRAM to maintain stabile. Where SRAM cells require increased speed, a single tensile stress liner can be implemented.
摘要翻译：单个应力衬垫施加在不同类型的半导体器件上。单应力衬垫通过消除会议面积避免双重/混合应力衬垫方案的问题。单个应力衬垫可以是拉伸或压缩的。在一个实施例中，半导体器件包括具有许多NFET和PFET的静态随机存取存储器（SRAM）单元。在这种情况下，压电衬垫放置在SRAM单元上，这对于其中的NFET通常不是理想的，但是对于SRAM单元来说是理想的，因为SRAM的继续小型化通常需要NSTS缓慢以使SRAM保持稳定。在SRAM单元需要增加速度的情况下，可以实现单个拉伸应力衬垫。

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