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1. 发明授权

US09614024B2 Fractal structures for MEMS variable capacitors 有权
公开(公告)号：US09614024B2
公开(公告)日：2017-04-04
申请号：US14239346
申请日：2012-08-21
申请人： Amro M. Elshurafa , Ahmed Gomaa Ahmed Radwan , Ahmed A. Emira , Khaled Nabil Salama
发明人： Amro M. Elshurafa , Ahmed Gomaa Ahmed Radwan , Ahmed A. Emira , Khaled Nabil Salama
IPC分类号： H01G5/00 , H01G7/00 , H01L49/02 , H01G5/18 , H01G5/16 , H01G13/00
CPC分类号： H01L28/40 , H01G5/16 , H01G5/18 , H01G7/00 , H01G13/00 , H01L28/86 , Y10T29/43
摘要： In accordance with the present disclosure, one embodiment of a fractal variable capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure, wherein the capacitor body has an upper first metal plate with a fractal shape separated by a vertical distance from a lower first metal plate with a complementary fractal shape; and a substrate above which the capacitor body is suspended.

2. 发明授权

US09349786B2 Fractal structures for fixed MEMS capacitors 有权
标题翻译：固定MEMS电容器的分形结构
公开(公告)号：US09349786B2
公开(公告)日：2016-05-24
申请号：US14239234
申请日：2012-08-17
申请人： Amro M. Elshurafa , Ahmed Gomaa Ahmed Radwan , Ahmed A. Emira , Khaled Nabil Salama
发明人： Amro M. Elshurafa , Ahmed Gomaa Ahmed Radwan , Ahmed A. Emira , Khaled Nabil Salama
IPC分类号： H01L21/02 , H01L49/02 , H01G5/18 , H01G5/16 , H01G7/00 , H01G13/00
CPC分类号： H01L28/40 , H01G5/16 , H01G5/18 , H01G7/00 , H01G13/00 , H01L28/86 , Y10T29/43
摘要： An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned.
摘要翻译：分形固定电容器的实施例包括在微机电系统（MEMS）结构中的电容器体。电容器主体具有与具有分形形状的第二板分隔开与水平距离分形的第一板。第一板和第二板在同一平面内。这种分形固定电容器还包括基板，电容器本体位于该基板上。

3. 发明授权

US09600238B2 Fully digital chaotic differential equation-based systems and methods 有权
公开(公告)号：US09600238B2
公开(公告)日：2017-03-21
申请号：US13408388
申请日：2012-02-29
申请人： Ahmed Gomaa Ahmed Radwan , Mohammed Affan Zidan , Khaled Nabil Salama
发明人： Ahmed Gomaa Ahmed Radwan , Mohammed Affan Zidan , Khaled Nabil Salama
IPC分类号： G06F7/58 , H04L9/00 , H04L9/06
CPC分类号： G06F7/588 , G06F7/58 , G06F7/586 , H04L9/001 , H04L9/0656
摘要： Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

4. 发明申请

US20120226724A1 FULLY DIGITAL CHAOTIC DIFFERENTIAL EQUATION-BASED SYSTEMS AND METHODS 有权
标题翻译：全数字混沌差分方程系统及方法
公开(公告)号：US20120226724A1
公开(公告)日：2012-09-06
申请号：US13408388
申请日：2012-02-29
申请人： Ahmed Gomaa Ahmed Radwan , Mohammed Affan Zidan , Khaled Nabil Salama
发明人： Ahmed Gomaa Ahmed Radwan , Mohammed Affan Zidan , Khaled Nabil Salama
IPC分类号： G06F17/13 , G06F17/10 , G06F7/58 , G06F7/48 , G06F5/01
CPC分类号： G06F7/588 , G06F7/58 , G06F7/586 , H04L9/001 , H04L9/0656
摘要： Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.
摘要翻译：提供了用于全数字混沌微分方程的系统和方法的各种实施例。在一个实施例中，数字电路包括数字状态寄存器和配置成从两个或更多个数字状态寄存器获得第一值的一个或多个数字逻辑模块; 基于获得的第一值和混沌微分方程确定第二值; 并提供第二值以设置多个数字状态寄存器之一的状态。在另一个实施例中，数字电路包括数字状态寄存器，数字逻辑模块，被配置为从数字移位寄存器的子集获得输出，并且基于混沌微分方程来提供输入，用于设置至少一个子集的状态数字移位寄存器和配置为提供用于操作数字移位寄存器的时钟信号的数字时钟。

5. 发明申请

US20120123750A1 Fractional Order Element Based Impedance Matching 有权
标题翻译：基于分数阶元件的阻抗匹配
公开(公告)号：US20120123750A1
公开(公告)日：2012-05-17
申请号：US13288135
申请日：2011-11-03
申请人： Ahmed Gomaa Ahmed Radwan , Atif Shamim , Khaled N. Salama
发明人： Ahmed Gomaa Ahmed Radwan , Atif Shamim , Khaled N. Salama
IPC分类号： G06F17/10
CPC分类号： H03H7/38 , H01P5/00
摘要： Disclosed are various embodiments of methods and systems related to fractional order element based impedance matching. In one embodiment, a method includes aligning a traditional Smith chart (|α|=1) with a fractional order Smith chart (|α|≠1). A load impedance is located on the traditional Smith chart and projected onto the fractional order Smith chart. A fractional order matching element is determined by transitioning along a matching circle of the fractional order Smith chart based at least in part upon characteristic line impedance. In another embodiment, a system includes a fractional order impedance matching application executed in a computing device. The fractional order impedance matching application includes logic that obtains a first set of Smith chart coordinates at a first order, determines a second set of Smith chart coordinates at a second order, and determines a fractional order matching element from the second set of Smith chart coordinates.
摘要翻译：公开了与基于分数阶单元的阻抗匹配相关的方法和系统的各种实施例。在一个实施例中，一种方法包括将传统史密斯圆图（|α| = 1）与分数阶史密斯圆图（|α|≠1）进行对齐。负载阻抗位于传统史密斯圆图上，并投影到分数阶史密斯图上。至少部分地基于特征线路阻抗，通过沿分数阶史密斯圆图的匹配圆转换来确定分数阶匹配元素。在另一个实施例中，系统包括在计算设备中执行的分数阶阻抗匹配应用。分数阶阻抗匹配应用包括以第一阶获得第一组史密斯圆图坐标的逻辑，以第二阶确定第二组史密斯圆图坐标，并从第二组史密斯圆图坐标确定分数阶匹配元素。

6. 发明授权

US08762114B2 Fractional order element based impedance matching 有权
标题翻译：基于分数阶元件的阻抗匹配
公开(公告)号：US08762114B2
公开(公告)日：2014-06-24
申请号：US13288135
申请日：2011-11-03
申请人： Khaled N. Salama , Ahmed Gomaa Ahmed Radwan , Atif Shamim
发明人： Khaled N. Salama , Ahmed Gomaa Ahmed Radwan , Atif Shamim
IPC分类号： G06F7/60
CPC分类号： H03H7/38 , H01P5/00
摘要： Disclosed are various embodiments of methods and systems related to fractional order element based impedance matching. In one embodiment, a method includes aligning a traditional Smith chart (|α|=1) with a fractional order Smith chart (|α|≠1). A load impedance is located on the traditional Smith chart and projected onto the fractional order Smith chart. A fractional order matching element is determined by transitioning along a matching circle of the fractional order Smith chart based at least in part upon characteristic line impedance. In another embodiment, a system includes a fractional order impedance matching application executed in a computing device. The fractional order impedance matching application includes logic that obtains a first set of Smith chart coordinates at a first order, determines a second set of Smith chart coordinates at a second order, and determines a fractional order matching element from the second set of Smith chart coordinates.
摘要翻译：公开了与基于分数阶单元的阻抗匹配相关的方法和系统的各种实施例。在一个实施例中，一种方法包括将传统史密斯圆图（|α| = 1）与分数阶史密斯圆图（|α|≠1）进行对齐。负载阻抗位于传统史密斯圆图上，并投影到分数阶史密斯图上。至少部分地基于特征线路阻抗，通过沿分数阶史密斯圆图的匹配圆转换来确定分数阶匹配元素。在另一个实施例中，系统包括在计算设备中执行的分数阶阻抗匹配应用。分数阶阻抗匹配应用包括以第一阶获得第一组史密斯圆图坐标的逻辑，以第二阶确定第二组史密斯圆图坐标，并从第二组史密斯圆图坐标确定分数阶匹配元素。

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