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1. 发明申请

US20050209162A1 Methods for monitoring IL-18 审中-公开
标题翻译：监测IL-18的方法
公开(公告)号：US20050209162A1
公开(公告)日：2005-09-22
申请号：US10985641
申请日：2004-11-10
申请人： Amit Roy , Matthew Harding , John Alam , John Randle
发明人： Amit Roy , Matthew Harding , John Alam , John Randle
IPC分类号： A61K38/04 , C07D207/16 , C07D405/12 , G01N33/00 , G01N33/68
CPC分类号： G01N33/6869 , A61K38/04 , C07D207/16 , C07D405/12 , G01N2333/54 , G01N2333/545 , G01N2800/52 , Y02A50/411 , Y02A50/58
摘要： This invention relates to methods for monitoring IL-18.
摘要翻译：本发明涉及用于监测IL-18的方法。

2. 发明申请

US20090215856A1 Methods for monitoring IL-18 审中-公开
标题翻译：监测IL-18的方法
公开(公告)号：US20090215856A1
公开(公告)日：2009-08-27
申请号：US12386933
申请日：2009-04-24
申请人： Amit Roy , Matthew W. Harding , John Alam , John Randle
发明人： Amit Roy , Matthew W. Harding , John Alam , John Randle
IPC分类号： A61K31/40 , G01N33/53 , A61P43/00
CPC分类号： G01N33/6869 , A61K38/04 , C07D207/16 , C07D405/12 , G01N2333/54 , G01N2333/545 , G01N2800/52 , Y02A50/411 , Y02A50/58
摘要： This invention relates to methods for monitoring IL-18.
摘要翻译：本发明涉及用于监测IL-18的方法。

3. 发明申请

US20150316950A1 DUAL-EDGE GATED CLOCK SIGNAL GENERATOR 有权
标题翻译：双边门控时钟信号发生器
公开(公告)号：US20150316950A1
公开(公告)日：2015-11-05
申请号：US14267933
申请日：2014-05-02
申请人： Amit Kumar Dey , Himanshu Mangal , Kulbhushan Misri , Amit Roy , Vijay Tayal , Chetan Verma
发明人： Amit Kumar Dey , Himanshu Mangal , Kulbhushan Misri , Amit Roy , Vijay Tayal , Chetan Verma
IPC分类号： G06F1/04 , H03K19/20
CPC分类号： G06F1/04 , H03K19/096 , H03K19/20
摘要： A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.
摘要翻译：时钟信号发生器提供门控时钟信号GCLK以触发双边缘触发电路的操作。当时钟门控信号/ EN被断言时，第一检测器产生一个第一检测器输出信号，该第一检测器输出信号被断言或取消断言作为分离或分别与输入时钟信号CLK和门控时钟信号GCLK 当时钟门控信号/ EN转换。当门控时钟信号/ EN被取消置位时，第二个检测器产生门控时钟信号GCLK的值，作为第一检测器输出信号的函数的值CLK或其补码/ CLK。当时钟选通信号/ EN被断言时，第二个检测器保持门控时钟信号GCLK当时钟门控信号/ EN从解除断言转变为有效时所具有的值。

4. 发明申请

US20150102839A1 LOW POWER INVERTER CIRCUIT 有权
标题翻译：低功率逆变器电路
公开(公告)号：US20150102839A1
公开(公告)日：2015-04-16
申请号：US14463673
申请日：2014-08-20
申请人： Amit Roy , Zhihong Cheng , Amit Kumar Dey , Vijay Tayal , Chetan Verma
发明人： Amit Roy , Zhihong Cheng , Amit Kumar Dey , Vijay Tayal , Chetan Verma
IPC分类号： H03K19/00 , H03K19/20 , H03K19/017
CPC分类号： H03K19/0013 , H03K19/0016 , H03K19/003 , H03K19/017 , H03K19/01707 , H03K19/20
摘要： A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
摘要翻译：低功率逆变器电路包括在其栅极端子处接收输入信号的第一和第二晶体管。第一和第二晶体管分别通过其源极端子连接到第三和第四晶体管。第三和第四晶体管分别与第五和第六晶体管并联连接。第三和第四晶体管被连续接通，并且当输入信号从一个状态转变到另一个状态时，第五和第六晶体管以这样的方式被控制，以减少流过第一和第二晶体管的短路电流。

5. 发明授权

US08803591B1 MOS transistor with forward bulk-biasing circuit 有权
标题翻译： MOS晶体管具有正向体积偏置电路
公开(公告)号：US08803591B1
公开(公告)日：2014-08-12
申请号：US14072809
申请日：2013-11-06
申请人： Amit Roy , Amit Kumar Dey , Kulbhushan Misri , Vijay Tayal , Chetan Verma
发明人： Amit Roy , Amit Kumar Dey , Kulbhushan Misri , Vijay Tayal , Chetan Verma
IPC分类号： H03K3/01 , G05F5/00 , H03K19/00 , G05F3/20
CPC分类号： G05F5/00 , G05F3/205 , H03K19/0027
摘要： Forward bulk biasing circuitry for PMOS and NMOS transistors is provided. The bulk biasing circuitry includes two N-type MOS transistors, two P-type MOS transistors, and two capacitors. The forward bias to a bulk terminal of a transistor increases a threshold voltage of a transistor, thereby reducing a transition time and improving the performance of the transistor. The forward bias is provided only when the transistor transitions from one state to another, thereby reducing leakage power dissipation during active and standby modes of an integrated circuit that includes the transistor.
摘要翻译：提供了用于PMOS和NMOS晶体管的正向体偏置电路。体偏置电路包括两个N型MOS晶体管，两个P型MOS晶体管和两个电容器。对晶体管的体积端子的正向偏压增加了晶体管的阈值电压，从而减小了转换时间并提高了晶体管的性能。仅当晶体管从一种状态转变到另一种状态时，才提供正向偏压，从而在包括晶体管的集成电路的有源和待机模式期间减少漏电功率损耗。

6. 发明授权

US08458210B2 Database load balancing through dynamic database routing 有权
标题翻译：数据库负载平衡通过动态数据库路由
公开(公告)号：US08458210B2
公开(公告)日：2013-06-04
申请号：US13102369
申请日：2011-05-06
申请人： Syed Arifuddin , Amit Roy , Venugopal Jagannathan
发明人： Syed Arifuddin , Amit Roy , Venugopal Jagannathan
IPC分类号： G06F17/30
CPC分类号： H04L67/1027 , G06F17/3056 , H04L67/146
摘要： A computing cluster may include servers that connect database servers. In one implementation, a server may receive a resource request from a client and extract a session identifier from the resource request. The server may determine, based on the session identifier, one of the database servers to use in fulfilling the resource request.
摘要翻译：计算集群可能包括连接数据库服务器的服务器。在一个实现中，服务器可以从客户端接收资源请求，并从资源请求中提取会话标识符。服务器可以基于会话标识符来确定在满足资源请求时使用的数据库服务器之一。

7. 发明授权

US09292651B2 System for partitioning integrated circuit design based on timing slack 有权
标题翻译：基于定时松弛的集成电路设计分区系统
公开(公告)号：US09292651B2
公开(公告)日：2016-03-22
申请号：US14195827
申请日：2014-03-03
申请人： Chetan Verma , Amit Kumar Dey , Ashis Maitra , Kulbhushan Misri , Amit Roy , Harkaran Singh , Vijay Tayal
发明人： Chetan Verma , Amit Kumar Dey , Ashis Maitra , Kulbhushan Misri , Amit Roy , Harkaran Singh , Vijay Tayal
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/84
摘要： A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.
摘要翻译：使用EDA工具的IC的物理设计方法包括识别具有过多正时序松弛的IC设计的元件。过多的定时松弛元件被放置在单独的分区中，然后修改多余的定时松弛元件的特性的参数以减少它们的超时间松弛，例如降低提供给单独隔板的电压，从而降低IC的功耗设计。

8. 发明授权

US08887120B1 Timing path slack monitoring system 有权
标题翻译：定时路径松弛监控系统
公开(公告)号：US08887120B1
公开(公告)日：2014-11-11
申请号：US14141473
申请日：2013-12-27
申请人： Chetan Verma , Amit Kumar Dey , Amit Roy , Vijay Tayal
发明人： Chetan Verma , Amit Kumar Dey , Amit Roy , Vijay Tayal
IPC分类号： G06F17/50 , G06F19/00 , G01R13/00 , G01R29/00 , G01R23/00 , H01L25/00 , H03K19/00
CPC分类号： G06F17/5031 , G01R13/00 , G01R23/00 , G01R29/00 , G06F19/00 , G06F2217/14 , G06F2217/70 , G06F2217/84 , H01L25/00 , H01L2924/0002 , H03K5/04 , H03K5/06 , H03K19/00 , H01L2924/00
摘要： An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.
摘要翻译：测量关键路径末端的定时松弛的片上定时松弛监视器包括具有在主机的Q输出上的抽头的主从触发器和耦合到触发器的逻辑模块，用于产生脉冲其宽度是松弛的函数。脉冲宽度收缩延迟线消除触发器输出上的毛刺，并且与数字积分器和计数器组合，还执行时间到数字转换操作，以确定定时路径松弛的值。确定的值由决策模块用于收益率分析。监视器可以将触发器输出上的毛刺脉冲与任何一个时钟周期的任何一个毛刺宽度区分开来。

9. 发明申请

US20050001660A1 Power-on reset circuit 审中-公开
标题翻译：上电复位电路
公开(公告)号：US20050001660A1
公开(公告)日：2005-01-06
申请号：US10874815
申请日：2004-06-22
申请人： Amit Roy
发明人： Amit Roy
IPC分类号： H03K17/00 , H03K17/22 , H03L7/00
CPC分类号： H03K17/223 , H03K2217/0036
摘要： An improved Power-On Reset (POR) circuit providing enhanced reliability and automatic power-down capability. The POR circuit includes a supply voltage sensing circuit, a delay element connected to the output of the supply voltage sensing circuit, and a switch that activates the output POR signal when the output of the delay element indicates a reduced supply voltage. The switch further acts to deactivate the POR output and provide feedback to reduce current through the supply voltage sensing circuit once the supply voltage is normal.
摘要翻译：改进的上电复位（POR）电路，提供增强的可靠性和自动掉电功能。 POR电路包括电源电压检测电路，连接到电源电压检测电路的输出的延迟元件，以及当延迟元件的输出指示降低的电源电压时激活输出POR信号的开关。一旦电源电压正常，该开关进一步用于停用POR输出并提供反馈以减少通过电源电压感测电路的电流。

10. 发明申请

US20160072488A1 VOLTAGE-DRIVER CIRCUIT WITH DYNAMIC SLEW RATE CONTROL 有权
标题翻译：具有动态睡眠速率控制的电压驱动电路
公开(公告)号：US20160072488A1
公开(公告)日：2016-03-10
申请号：US14480642
申请日：2014-09-09
申请人： Chetan Verma , Geetansh Arora , Amit Roy
发明人： Chetan Verma , Geetansh Arora , Amit Roy
IPC分类号： H03K5/12 , H03K5/1534 , H03K5/24
CPC分类号： H03K5/12 , H03K5/1534 , H03K5/24
摘要： A system for circuit for generating an output signal with a dynamically adjustable slew rate includes a sampler, an envelope detector, an envelope comparison and control circuit, and a voltage-driver circuit that includes output buffers for generating the output signal. The sampler generates a sampled signal indicative of the slew rate of the output signal. The envelope detector generates an envelope detection signal indicative of a peak value of the sampled signal. The envelope comparison and control circuit compares a voltage level of the envelope detection signal with various threshold voltage levels, and generates control signals. The voltage-driver circuit controls the operation states of the output buffers based on the control signals to dynamically adjust the slew rate of the output signal.
摘要翻译：一种用于产生具有动态可调压摆率的输出信号的电路系统，包括采样器，包络检波器，包络比较和控制电路以及包括用于产生输出信号的输出缓冲器的电压驱动器电路。采样器产生指示输出信号的转换速率的采样信号。包络检测器产生指示采样信号的峰值的包络检测信号。包络比较和控制电路将包络检测信号的电压电平与各种阈值电压电平进行比较，并产生控制信号。电压驱动电路基于控制信号控制输出缓冲器的动作状态，动态调整输出信号的转换速度。

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