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1. 发明授权

US4831594A Process and device for refreshing an array of dynamic memory cells during precharge of the column lines 失效
标题翻译：用于在列线的预充电期间刷新动态存储器单元阵列的过程和设备
公开(公告)号：US4831594A
公开(公告)日：1989-05-16
申请号：US911289
申请日：1986-09-25
申请人： Aman Khosrovi , Perry W. Lou , Ki S. Chang
发明人： Aman Khosrovi , Perry W. Lou , Ki S. Chang
IPC分类号： G11C11/406
CPC分类号： G11C11/406
摘要： The device refreshes the cells of an array of dynamic memory cells a row at a time during precharging of the bit or column lines. Normal access to read or write to the cells also refreshes them. Refresh circuits connect to the row line between the row address decoder and the cells, and include shift register stages connected to the row lines. A bit of one sense shifting through the stages indicates the row to be refreshed and a refresh signal connected to the stages times the refresh during the precharge. Using multiple, sequential refresh signals refreshes alternating rows of the cells.
摘要翻译：在位或列线的预充电期间，器件一次一行地刷新动态存储器单元阵列的单元。读取或写入单元格的正常访问也刷新它们。刷新电路连接到行地址解码器和单元之间的行线，并且包括连接到行线的移位寄存器级。通过这些阶段移位的一个感觉指示要刷新的行，并且在预充电期间连接到阶段的刷新信号乘以刷新。使用多个顺序刷新信号刷新单元格的交替行。

2. 发明授权

US4926176A Self-timing analog-to-digital converting system 失效
标题翻译：自定时模数转换系统
公开(公告)号：US4926176A
公开(公告)日：1990-05-15
申请号：US236505
申请日：1988-08-25
申请人： Lanny L. Lewyn , Perry W. Lou
发明人： Lanny L. Lewyn , Perry W. Lou
IPC分类号： H03M1/36 , H03K3/356 , H03K5/08 , H03M1/12 , H03M1/34
CPC分类号： H03K3/356104 , H03M1/125 , H03M1/365
摘要： A substantially constant current is divided between two lines in accordance with the relative values of an input voltage and a reference voltage respectively introduced to such lines. The currents through the first and second lines respectively charge first and second capacitances. The charges in the first and second capacitances respectively control the magnitudes of the currents flowing through first and second control members to charge the first and second capacitances. The control members are interconnected so that any difference between the flow of current through the control members and the associated capacitances between magnified. When the charge in an individual one of the capacitances reaches a particular value, a signal on an output terminal associated with the other capacitance changes from the first magnitude to a second magnitude. During this time, the signal associated with the first capacitance remains at substantially the first magnitude. A plurality of stages, including the comparators discussed above, compare the input voltage with progressive values of the reference voltage. Such stages are connected to successive pairs of comparators to indicate, on the basis of the relative magnitudes of the voltages on the output terminals of such comparators, whether the reference voltage is greater than the input voltage for both comparators in such pairs. A output signal is provided by the plurality only when one pair of comparators provides an output indicating that the input voltage is between the reference voltages connected to that pair of comparators.

3. 发明授权

US4628215A Drive circuit for substrate pump 失效
标题翻译：基板泵驱动电路
公开(公告)号：US4628215A
公开(公告)日：1986-12-09
申请号：US651140
申请日：1984-09-17
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H01L27/04 , G05F3/20 , G11C11/407 , H01L21/822 , H02M3/07 , H03L1/00 , G05F3/24 , H03K17/693
CPC分类号： G05F3/205
摘要： A substrate pump circuit for generating a negative bias on the substrate of a semiconductor device employs a capacitor coupling an oscillator output to a pump node, and MOS diodes coupling the pump node to a ground terminal and to the substrate node; the MOS diode for the substrate node is reconfigured as an active switch, controlled by a complementary pump circuit. This circuit allows transfer of more charge from the pumping capacitor to the substrate capacitance on each pump cycle. Also, pumped charge is delivered directly to the substrate through ohmic connections, rather than through forward biased injecting junctions.
摘要翻译：用于在半导体器件的衬底上产生负偏压的衬底泵电路使用将振荡器输出耦合到泵节点的电容器，以及将泵节点耦合到接地端子和衬底节点的MOS二极管; 用于衬底节点的MOS二极管被重新配置为由互补泵电路控制的有源开关。该电路允许在每个泵循环中将更多的电荷从泵送电容转移到衬底电容。此外，泵浦电荷通过欧姆连接而不是通过正向偏置的注入结直接传递到衬底。

4. 发明授权

US4164031A Memory system 失效
标题翻译：内存系统
公开(公告)号：US4164031A
公开(公告)日：1979-08-07
申请号：US745157
申请日：1976-11-26
申请人： Perry W. Lou , Charles P. Grant, Jr., deceased
发明人： Perry W. Lou , Charles P. Grant, Jr., deceased
IPC分类号： G11C8/04 , G11C8/12 , G11C11/405 , G11C11/408 , G11C11/40 , G11C13/00
CPC分类号： G11C11/405 , G11C11/4085 , G11C8/04 , G11C8/12
摘要： Disclosed is a memory system for storing digital data; the memory system of the type which may be implemented, for instance, in an electronic microprocessor or calculator system. The memory comprises an array of transistor memory cells arranged in columns and rows. Column conductors are provided for supplying digital information to each column of such cells and row conductors are provided for enabling each row of cells to store digital information being received on the column conductors. A commutator is provided for successively supplying enabling signals to the row conductors and another commutator is provided for successfully connecting the column conductors with an input/output bus in the memory system. The provision of the commutators with the array of memory cells causes the data, when stored as a word of data, to occupy a register arranged in essentially a diagonal pattern through the array.
摘要翻译：公开了一种用于存储数字数据的存储系统; 可以例如在电子微处理器或计算器系统中实现的类型的存储器系统。存储器包括以列和行排列的晶体管存储单元阵列。列导体被提供用于向这些单元的每列提供数字信息，并且提供行导体用于使每一行单元能够存储正在接收到列导体上的数字信息。提供了一个换向器，用于连续地向行导体提供使能信号，并且提供了另一个换向器，用于将列导体与存储器系统中的输入/输出总线成功连接。具有存储器单元阵列的换向器的提供使得当作为数据字存储时，数据占据通过阵列以基本上对角线图案布置的寄存器。

5. 发明授权

US5406219A Differential-to-single-ended converter 失效
标题翻译：差分到单端转换器
公开(公告)号：US5406219A
公开(公告)日：1995-04-11
申请号：US16131
申请日：1993-02-10
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H03F3/45 , H03K5/24 , H03K19/017 , H03K19/094 , H03K5/153
CPC分类号： H03F3/45076 , H03K19/01707 , H03K19/09432 , H03K5/2481
摘要： First and second transistors respectively receive differential input signals each having first and second logic levels and respectively produce resultant currents dependent upon the levels of the input signals. The transistors may be CMOS transistors of the n-type with substantially identical characteristics. The input signals may be introduced to the gates of these transistors and the resultant currents may be produced at the drains of these transistors. Third and fourth transistors may receive the resultant currents. The third and fourth transistors may be CMOS transistors of the n-type with substantially identical characteristics. The resultant voltage at the first transistor may be introduced in a modified form to the third and fourth transistors to regulate the resultant voltage introduced to the third transistor and to expedite the response of the fourth transistor. The modification may be an inversion of the resultant voltage at the first transistor, the inversion being produced by an amplifier-inverter in a servo loop with the third transistor. The currents on the drains of the first and second transistors may be respectively introduced to the sources of the third and fourth transistors. The modified (or inverted) voltage from the drain of the first transistor may be introduced to the gates of the third and fourth transistors. An output voltage may be provided at the source of the fourth transistor. The output voltage may be inverted as by an amplifier-inverter having characteristics substantially identical to those of the amplifier-inverter in the servo loop.
摘要翻译：第一和第二晶体管分别接收各自具有第一和第二逻辑电平的差分输入信号，并且分别产生取决于输入信号电平的合成电流。晶体管可以是具有基本相同特性的n型CMOS晶体管。输入信号可以被引入到这些晶体管的栅极，并且所得到的电流可以在这些晶体管的漏极处产生。第三和第四晶体管可以接收所得的电流。第三和第四晶体管可以是具有基本相同特性的n型CMOS晶体管。第一晶体管处的合成电压可以以修改形式引入第三和第四晶体管，以调节引入第三晶体管的合成电压并加速第四晶体管的响应。该修改可以是在第一晶体管处的合成电压的反转，反转由具有第三晶体管的伺服环路中的放大器 - 反相器产生。可以将第一和第二晶体管的漏极上的电流分别引入第三和第四晶体管的源极。来自第一晶体管的漏极的修正（或反转）电压可以被引入第三和第四晶体管的栅极。可以在第四晶体管的源极处提供输出电压。输出电压可以由具有与伺服环路中的放大器 - 反相器基本相同的特性的放大器 - 反相器反转。

6. 发明授权

US5227714A Voltage regulator 失效
标题翻译：电压稳压器
公开(公告)号：US5227714A
公开(公告)日：1993-07-13
申请号：US772218
申请日：1991-10-07
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G05F1/56 , G05F1/46 , G05F3/24 , G05F3/26
CPC分类号： G05F3/24 , G05F1/465
摘要： A system for regulating an output voltage to a particular value includes a control transistor which produces an output voltage when energized by an energizing voltage. A voltage divider formed as by a pair of transistors with a particular ratio of transconductances divides the magnitude of this output voltage by a ratio related to the ratio of the transconductances. The transistors in the voltage divider may be respectively CMOS n- and p- transistors. The divided output voltage is introduced to a comparator (formed as from a pair of transistors) for comparison with a fixed reference voltage obtained as from a resistance ladder energized by the energizing voltage. The comparator introduces voltages to a comparator amplifier in accordance with such comparison. The comparator amplifier may include a transistor which produces changes in a current related to changes in the divided output voltage. The comparator amplifier may further include a current mirror which provides changes in a current related to changes in the current through the amplifier transistor. The current changes in the current mirror cause changes to be produced in a voltage (e.g. error voltage) from the current mirror. These error voltage changes are introduced to the control transistor to regulate the output voltage to the particular value.

7. 发明授权

US4280271A Three level interconnect process for manufacture of integrated circuit devices 失效
标题翻译：用于制造集成电路器件的三级互连工艺
公开(公告)号：US4280271A
公开(公告)日：1981-07-28
申请号：US83702
申请日：1979-10-11
申请人： Perry W. Lou , James E. Ponder , Graham S. Tubbs
发明人： Perry W. Lou , James E. Ponder , Graham S. Tubbs
IPC分类号： H01L21/033 , H01L21/336 , H01L21/768 , H01L29/08 , H01L21/265 , H01L21/225
CPC分类号： H01L29/66575 , H01L21/033 , H01L21/768 , H01L29/0847
摘要： An improved MOS device and method of making it are provided which utilize basically the standard N-chanel self-aligned silicon gate structure and process with implants for self-alignment, modified to allow three levels of interconnects. A P-type substrate is used as the starting material, with N+ source and drain regions defined prior to a polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.
摘要翻译：提供了一种改进的MOS器件及其制造方法，其基本上利用标准N-chanel自对准硅栅极结构和具有用于自对准的植入物的工艺，经修改以允许三个级别的互连。使用P型衬底作为起始材料，其中N +源极和漏极区域在多晶硅栅极之前定义; 因此源极和漏极可能在多晶硅下运行。多晶硅定义后的自对准植入物产生自对准栅极的优点。

8. 发明授权

US07064575B2 Method and system for adaptively controlling output driver impedance 失效
标题翻译：自适应控制输出驱动器阻抗的方法和系统
公开(公告)号：US07064575B2
公开(公告)日：2006-06-20
申请号：US10931646
申请日：2004-08-31
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H03K19/0005
摘要： An adaptive output driver circuit utilizes an initial point matched impedance model to match the impedance of an output driver to the transmission line and produce an initial step voltage into the transmission line that is half of the desired final voltage. The driver output impedance is controlled by comparing a model of the actual working output stage to a target resistance given by the user. Control signals used to calibrate the impedance of the model to match the target are also used to adjust the working output buffer, so that when the impedance of the model matches the target, the impedance of the working buffer also matches the target impedance.
摘要翻译：自适应输出驱动器电路利用初始点匹配阻抗模型将输出驱动器的阻抗与传输线相匹配，并且产生到传输线中的初始阶跃电压，其为期望最终电压的一半。通过将实际工作输出级的模型与用户给出的目标电阻进行比较来控制驱动器输出阻抗。用于校准模型的阻抗以匹配目标的控制信号也用于调整工作输出缓冲器，使得当模型的阻抗与目标匹配时，工作缓冲器的阻抗也与目标阻抗匹配。

9. 发明授权

US5051618A High voltage system using enhancement and depletion field effect transistors 失效
标题翻译：高压系统采用增强型和耗尽型场效应晶体管
公开(公告)号：US5051618A
公开(公告)日：1991-09-24
申请号：US468917
申请日：1990-01-23
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H03K17/10 , H03K17/687
CPC分类号： H03K17/102 , H03K17/6871
摘要： An enhancement mode field effect transistor and a depletion mode field effect transistor are connected in a circuit to provide for a conductivity of the transistors during a first polarity in an alternating voltage and to provide for a non-conductivity of the transistors during a second polarity in the alternating voltage. The circuit also provides for the continued and proper operation of the circuit even when voltages having a magnitude greater than the breakdown voltage of the enhancement mode field effect transistor are applied to the circuit. Each of the transistors may have a source, a gate and a drain. The gates of the transistors receive an alternating voltage of one polarity at the same time that the drain of the depletion mode field effect transistor receives a voltage of the opposite polarity. The source of the depletion mode field effect transistor and the drain of the enhancement mode field effect transistor are common. The source of the enhancement mode field effect transistor may receive a reference potential such as ground. The transistors are conductive during the application of a positive voltage to their gates and are non-conductive during the application of a negative voltage to their gates. When the transistors are non-conductive, the depletion mode transistor prevents the voltage on the drain of the enhancement mode field effect transistor from exceeding the breakdown value.
摘要翻译：增强型场效应晶体管和耗尽型场效应晶体管连接在电路中以在交流电压的第一极性期间提供晶体管的导电性，并且在第二极性期间提供晶体管的非导电性交流电压。即使当具有大于增强型场效应晶体管的击穿电压的电压的电压被施加到电路时，该电路还提供电路的连续且正常的操作。每个晶体管可以具有源极，栅极和漏极。在耗尽型场效应晶体管的漏极接收相反极性的电压的同时，晶体管的栅极接收一个极性的交流电压。耗尽型场效应晶体管的源极和增强型场效应晶体管的漏极是常见的。增强型场效应晶体管的源极可以接收诸如地的参考电位。在向它们的栅极施加正电压时，晶体管是导电的，并且在向它们的栅极施加负电压期间是不导电的。当晶体管不导通时，耗尽型晶体管防止增强型场效应晶体管的漏极上的电压超过击穿值。

10. 发明授权

US4454591A Interface system for bus line control 失效
标题翻译：接口系统，用于总线控制
公开(公告)号：US4454591A
公开(公告)日：1984-06-12
申请号：US154560
申请日：1980-05-29
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G06F12/06 , G06F15/78 , G06F13/00 , G06F3/00
CPC分类号： G06F15/7867 , G06F12/063
摘要： An external I/O pull down latch and a system embodiment thereof. The interface system has a bus line including of a first means for providing an output at a fixed voltage level on said bus line for a first time interval, and a second means coupled to said bus line for maintaining the bus line at the fixed voltage level subsequent to the first time interval. In the preferred embodiment, the second means is comprised of said external I/O pull down latch. The present invention is a replacement for traditional pull up or pull down resistors in controlling I/O bus lines coupling main processor circuits with external memory circuits. In the preferred embodiment, the external I/O pull down latch is comprised of a read-write memory bit cell, sized such that it may be overdriven by any driver attached to the bus line.
摘要翻译：外部I / O下拉锁存器及其系统实施例。接口系统具有总线线路，该总线线路包括用于在第一时间间隔内在所述总线上提供固定电压电平的输出的第一装置，以及耦合到所述总线线路的第二装置，用于将总线线路保持在固定电压电平在第一时间间隔之后。在优选实施例中，第二装置包括所述外部I / O下拉锁存器。本发明是用于控制将主处理器电路与外部存储器电路耦合的I / O总线的传统上拉或下拉电阻的替代。在优选实施例中，外部I / O下拉锁存器包括读写存储器位单元，其大小使得其可能被连接到总线线路的任何驱动器过载。

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