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1. 发明授权

US5602495A Apparatus for providing an output voltage with substantially identical rising and falling characteristics 失效
标题翻译：用于提供具有基本相同的上升和下降特性的输出电压的装置
公开(公告)号：US5602495A
公开(公告)日：1997-02-11
申请号：US434973
申请日：1995-05-04
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G05F3/24 , H03K19/0185 , H03K19/0948
CPC分类号： G05F3/247 , H03K19/018521
摘要： An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than the bias voltage less the pass transistor threshold. The first control voltage corresponds to the input voltage for input voltages less than the bias voltage less the pass transistor threshold. The first control voltage is inverted to produce a second control voltage having the first control voltage amplitude for small amplitude values of the first control voltage and having transition times and amplitudes of the first control voltage for large amplitude values of the first control voltage. A circuit differentially responds to the control voltages to produce an output voltage which rises and falls in accordance with the variations in the input voltage. The output voltage is servoed to limit the rises and falls. The output voltage has substantially the same wave shape, and substantially the same delay relative to the input voltage, for rising and falling values.
摘要翻译：逆变器在第一端接收具有特定幅度（例如1.5V）的激励电压，并在第二端产生电压。接收和产生的电压被差分地引入到产生与第二端子电压相关的单端偏压（例如3V）的级。伺服偏置电压以调节第二端电压（例如1.5V）和偏置电压（例如3V），而不管施加电压变化。响应于偏置电压和可变输入电压，缓冲器中的传输晶体管产生与偏置电压不同的第一控制电压，通过传输晶体管阈值电压，用于输入电压大于偏置电压，小于通过晶体管阈值。第一控制电压对应于输入电压的输入电压小于偏置电压小于通过晶体管阈值。第一控制电压被反相以产生对于第一控制电压的小振幅值具有第一控制电压幅度的第二控制电压，并且对于第一控制电压的大振幅值具有转换时间和第一控制电压的幅度。电路对控制电压进行差分响应以产生根据输入电压的变化而上升和下降的输出电压。输出电压被伺服以限制上升和下降。对于上升和下降值，输出电压具有基本上相同的波形，并且相对于输入电压基本相同的延迟。

2. 发明授权

US5486778A Input buffer for translating TTL levels to CMOS levels 失效
标题翻译：用于提供具有相同相同上升和下降特性的输出电压的装置。
公开(公告)号：US5486778A
公开(公告)日：1996-01-23
申请号：US028999
申请日：1993-03-10
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G05F3/24 , H03K19/0185 , H03K19/0948
CPC分类号： G05F3/247 , H03K19/018521
摘要： An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than a value equal to the bias voltage less the pass transistor threshold, and corresponding to the input voltage for input voltages less than the bias voltage less the pass transistor threshold. The first control voltage is inverted to produce a second control voltage having the amplitude of the first control voltage for small amplitude values of the first control voltage, and having transition times and amplitudes of the first control voltage for large amplitude values of the first control voltage. A circuit differentially responds to the control voltage to produce an output voltage which rises and falls in accordance with the variations in the input voltage. The output voltage is servoed to limit the rises and falls.
摘要翻译：逆变器在第一端接收具有特定幅度（例如1.5V）的激励电压，并在第二端产生电压。接收和产生的电压被差分地引入到产生与第二端子电压相关的单端偏压（例如3V）的级。伺服偏置电压以调节第二端电压（例如1.5V）和偏置电压（例如3V），而不管施加电压变化。响应于偏置电压和可变输入电压，缓冲器中的传输晶体管产生与偏置电压不同的第一控制电压，通过用于输入电压的传输晶体管阈值电压，该输入电压大于等于偏置电压的值小于传输晶体管阈值，并且对应于输入电压的输入电压小于偏置电压小于通过晶体管阈值。第一控制电压被反相以产生对于第一控制电压的小振幅值具有第一控制电压的振幅的第二控制电压，并且对于第一控制电压的大振幅值具有转换时间和第一控制电压的幅度。电路对控制电压进行差分响应以产生根据输入电压的变化而上升和下降的输出电压。输出电压被伺服以限制上升和下降。

3. 发明授权

US4831594A Process and device for refreshing an array of dynamic memory cells during precharge of the column lines 失效
标题翻译：用于在列线的预充电期间刷新动态存储器单元阵列的过程和设备
公开(公告)号：US4831594A
公开(公告)日：1989-05-16
申请号：US911289
申请日：1986-09-25
申请人： Aman Khosrovi , Perry W. Lou , Ki S. Chang
发明人： Aman Khosrovi , Perry W. Lou , Ki S. Chang
IPC分类号： G11C11/406
CPC分类号： G11C11/406
摘要： The device refreshes the cells of an array of dynamic memory cells a row at a time during precharging of the bit or column lines. Normal access to read or write to the cells also refreshes them. Refresh circuits connect to the row line between the row address decoder and the cells, and include shift register stages connected to the row lines. A bit of one sense shifting through the stages indicates the row to be refreshed and a refresh signal connected to the stages times the refresh during the precharge. Using multiple, sequential refresh signals refreshes alternating rows of the cells.
摘要翻译：在位或列线的预充电期间，器件一次一行地刷新动态存储器单元阵列的单元。读取或写入单元格的正常访问也刷新它们。刷新电路连接到行地址解码器和单元之间的行线，并且包括连接到行线的移位寄存器级。通过这些阶段移位的一个感觉指示要刷新的行，并且在预充电期间连接到阶段的刷新信号乘以刷新。使用多个顺序刷新信号刷新单元格的交替行。

4. 发明授权

US4656369A Ring oscillator substrate bias generator with precharge voltage feedback control 失效
标题翻译：环形振荡器基板偏置发生器，具有预充电电压反馈控制
公开(公告)号：US4656369A
公开(公告)日：1987-04-07
申请号：US651401
申请日：1984-09-17
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G05F3/20 , H03K3/03 , H03B5/24
CPC分类号： G05F3/205 , H03K3/0315
摘要： A generator circuit for producing a negative bias voltage on a substrate for a semiconductor device employs a multistage on-chip oscillator driving individul charge pump circuits for each stage. The oscillator may produce a frequency related to the value of the negative bias, using a feedback circuit. Each of the charge pump circuits includes a capacitor and an MOS diode coupled to the substrate and another diode coupled to the ground terminal of the supply.
摘要翻译：用于在半导体器件的衬底上产生负偏置电压的发生器电路采用驱动单个电荷泵电路的多级片上振荡器。振荡器可以使用反馈电路产生与负偏压值相关的频率。电荷泵电路中的每一个包括耦合到基板的电容器和MOS二极管，以及耦合到电源的接地端子的另一个二极管。

5. 发明授权

US4447881A Data processing system integrated circuit having modular memory add-on capacity 失效
标题翻译：具有模块化存储器附加容量的数据处理系统集成电路
公开(公告)号：US4447881A
公开(公告)日：1984-05-08
申请号：US154335
申请日：1980-05-29
申请人： George L. Brantingham , Perry W. Lou , Lawrence J. Housey , Graham S. Tubbs , Jeffrey R. Teza
发明人： George L. Brantingham , Perry W. Lou , Lawrence J. Housey , Graham S. Tubbs , Jeffrey R. Teza
IPC分类号： G06F12/06 , G06F15/78 , G06F15/46
CPC分类号： G06F12/063
摘要： A method of designing and manufacturing a modular integrated circuit for a 4 bit microcomputer family utilizing a modular concept which is adaptable for a variety of applications and specific circuit desgins. The modular circuit is designed as a large block of cells which contains an ALU, instruction decoder, bus structure and a small amount of RAM and ROM as well as ROM control logic. In addition, the block contains attachment points for additional ROM and RAM and for special input/output devices such as I/O bus, timekeeping, A-D, D-A, display drive, communication ports and general purpose control lines.
摘要翻译：一种利用适用于各种应用和特定电路设计的模块化概念设计和制造用于4位微机系列的模块化集成电路的方法。模块化电路被设计为包含ALU，指令解码器，总线结构和少量RAM和ROM以及ROM控制逻辑的大块单元。此外，该块还包含用于附加ROM和RAM以及I / O总线，计时，A-D，D-A，显示驱动器，通信端口和通用控制线等特殊输入/输出设备的连接点。

6. 发明授权

US5789972A Regulated reference voltage generator having feedback to provide a stable voltage 失效
标题翻译：具有反馈以提供稳定电压的稳压基准电压发生器
公开(公告)号：US5789972A
公开(公告)日：1998-08-04
申请号：US730097
申请日：1996-10-15
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G05F3/24 , H03K19/0185 , G05F1/10
CPC分类号： G05F3/247 , H03K19/018521
摘要： An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than the bias voltage less the pass transistor threshold. The first control voltage corresponds to the input voltage for input voltages less than the bias voltage less the pass transistor threshold. The first control voltage is inverted to produce a second control voltage having the first control voltage amplitude for small amplitude values of the first control voltage and having transition times and amplitudes of the first control voltage for large amplitude values of the first control voltage. A circuit differentially responds to the control voltages to produce an output voltage which rises and falls in accordance with the variations in the input voltage. The output voltage is servoed to limit the rises and falls. The output voltage has substantially the same wave shape, and substantially the same delay relative to the input voltage, for rising and falling values.
摘要翻译：逆变器在第一端接收具有特定幅度（例如1.5V）的激励电压，并在第二端产生电压。接收和产生的电压被差分地引入到产生与第二端子电压相关的单端偏压（例如3V）的级。伺服偏置电压以调节第二端电压（例如1.5V）和偏置电压（例如3V），而不管施加电压变化。响应于偏置电压和可变输入电压，缓冲器中的传输晶体管产生与偏置电压不同的第一控制电压，通过传输晶体管阈值电压，用于输入电压大于偏置电压，小于通过晶体管阈值。第一控制电压对应于输入电压的输入电压小于偏置电压小于通过晶体管阈值。第一控制电压被反相以产生对于第一控制电压的小振幅值具有第一控制电压幅度的第二控制电压，并且对于第一控制电压的大振幅值具有转换时间和第一控制电压的幅度。电路对控制电压进行差分响应以产生根据输入电压的变化而上升和下降的输出电压。输出电压被伺服以限制上升和下降。对于上升和下降值，输出电压具有基本上相同的波形，并且相对于输入电压基本相同的延迟。

7. 发明授权

US5338990A Regulated delay line 失效
标题翻译：调节延时线
公开(公告)号：US5338990A
公开(公告)日：1994-08-16
申请号：US019784
申请日：1993-02-19
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H03K5/00 , H03K5/13 , H03K5/159 , H03K3/01
CPC分类号： H03K5/131 , H03K2005/00097 , H03K2005/00136
摘要： Three delay lines may have common characteristics. The first delay line delays the rising edge of an input signal and a first inverter inverts this signal to provide a falling edge. A second inverter inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line in a second path with the second inverter. The signals from the two paths may be introduced to a comparator which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal. This voltage is introduced to the first and second delay lines to adjust their delay to minimize the time difference in the falling edges of the signals from these lines. This voltage is also introduced to the third delay line to adjust its delay in accordance with the adjustments in the delays in the first and second lines. In this way, the third delay line provides the same time for rising edges and falling edges in data signals introduced to the line.
摘要翻译：三条延迟线可能具有共同特征。第一延迟线延迟输入信号的上升沿，第一反相器反相该信号以提供下降沿。第二反相器反转输入信号的上升沿，产生下降沿，该下降沿与第二反相器以第二路径被引入第二延迟线。来自两个路径的信号可以被引入比较器，该比较器产生具有逻辑电平的控制信号，该逻辑电平取决于两个路径中的信号的下降沿的相对时间。例如，当下降沿首先在第一路径中发生时，控制信号可以具有第一逻辑电平，并且当下降沿首先在第二路径中发生时，控制信号可能具有第二逻辑电平。来自电荷泵的电压根据控制信号的逻辑电平进行调节。该电压被引入到第一和第二延迟线以调整它们的延迟以最小化来自这些线的信号的下降沿中的时间差。该电压也被引入第三延迟线，以根据第一和第二线中的延迟的调整来调整其延迟。以这种方式，第三延迟线为引入到线路的数据信号中的上升沿和下降沿提供相同的时间。

8. 发明授权

US4841252A System for compensating for offset voltages in comparators 失效
标题翻译：用于补偿比较器中偏移电压的系统
公开(公告)号：US4841252A
公开(公告)日：1989-06-20
申请号：US81910
申请日：1987-08-05
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H03F3/34 , H03F1/30
CPC分类号： H03F1/303
摘要： A variable input voltage is periodically introduced in first time periods to an amplifier such as a differential amplifier to obtain an output from the amplifier. The amplifier may receive a reference voltage at one input terminal and the input voltage at a second input terminal in the first time periods. The input to the amplifier is periodically shorted in second time periods alternating with the first time periods so that the reference voltage is applied to both input terminals. Any offset voltage from the amplifier in the second time period may be converted to a binary signal to indicate the polarity of the offset voltage. The binary signal may be introduced to a storage member such as a capacitance. The capacitance accumulates energy in accordance with the characteristics of the binary signal in successive ones of the second time periods. The energy in the capacitance is introduced to the output terminals of the amplifier in a direction to compensate for the offset voltage in the amplifier. First switches may prevent the energy in the capacitance from being introduced to the output terminals of the amplifier during the second time periods. Second switches may prevent the capacitance from being charged by the output from the amplifier during the first time periods.

9. 发明授权

US4115710A Substrate bias for MOS integrated circuit 失效
标题翻译： MOS集成电路的衬底偏置
公开(公告)号：US4115710A
公开(公告)日：1978-09-19
申请号：US754474
申请日：1976-12-27
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G11C11/413 , G05F3/20 , G06F15/02 , G06F15/78 , G11C11/407 , G11C11/4074 , G11C19/18 , G11C19/28 , H01L21/822 , H01L27/04 , H01L27/06 , H03K3/354 , H03K17/06 , H03K19/094 , H03K1/02 , H03K3/353
CPC分类号： H03K19/094 , G05F3/205 , G11C11/4074 , G11C19/184 , H03K3/354
摘要： A charge pump circuit for generating a substrate bias for MOS/LSI integrated circuit chips is provided, preferably for P-channel integrated circuits. The charge pump circuit includes an osicllator producing a square wave which is applied to a reference circuit that is also responsive to a threshold voltage Vt monitor. The reference circuit applies to a pump diode a square wave having a level responsive to the supply and thresholds. A zero voltage drop source follower connects the square wave to the diode to avoid loading. The threshold monitor forces the square wave to a high level when the threshold is below a certain value.
摘要翻译：提供用于产生用于MOS / LSI集成电路芯片的衬底偏置的电荷泵电路，优选用于P沟道集成电路。电荷泵电路包括产生方波的滤波器，其施加到也响应于阈值电压Vt监视器的参考电路。参考电路适用于泵浦二极管，具有响应于电源和阈值的电平的方波。零电压降源极跟随器将方波连接到二极管以避免加载。当阈值低于一定值时，阈值监视器将方波强制为高电平。

10. 发明授权

US4082966A MOS detector or sensing circuit 失效
标题翻译： MOS探测器或感应电路
公开(公告)号：US4082966A
公开(公告)日：1978-04-04
申请号：US754473
申请日：1976-12-27
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： G11C7/06 , G11C11/34 , G11C17/12 , H03K5/02 , H03K5/18 , G11C13/08 , G11C17/04 , H03K17/60
CPC分类号： H03K5/023 , G11C17/12 , G11C7/067
摘要： A detector circuit for MOS/LSI integrated circuit devices comprises a series transistor which has a sense clock applied to its gate and a gated capacitor connected between the gate and a sense node. The sense node and an input node may be precharged to a level at or near the supply. During the sense clock, the input and sense nodes are shunted together by the series transistor. If at the logic level of the supply, the gated capacitor is off and does not affect the circuit; if the input node decays toward the other logic level, the gated capacitor is on and the trailing edge of the sense clock causes the sense node to be switched to a full logic level.

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