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1. 发明申请

US20060197623A1 Method and apparatus for biasing a metal-oxide-semiconductor capacitor for capacitive tuning 失效
标题翻译：用于偏置用于电容调谐的金属氧化物半导体电容器的方法和装置
公开(公告)号：US20060197623A1
公开(公告)日：2006-09-07
申请号：US11070985
申请日：2005-03-03
申请人： Alvin Loke , Tin Wee , Robert Barnes , Kari Arave , Thomas Cynkar , James Pfiester
发明人： Alvin Loke , Tin Wee , Robert Barnes , Kari Arave , Thomas Cynkar , James Pfiester
IPC分类号： H03B5/12
CPC分类号： H03B5/04 , H03D13/004 , H03L7/0891 , H03L7/099 , H03L7/18 , H03L2207/06
摘要： A method and apparatus is presented for generating a reference voltage that biases a metal-oxide-semiconductor (MOS) transistor used as a varactor in capacitive tuning applications. In one embodiment, a biasing circuit is implemented. The biasing circuit comprises a diode-clamped FET and an element coupled to the diode-clamped FET at a connection point. The element produces a constant current through the diode-clamped FET. A voltage is produced at the connection point. The voltage is one gate overdrive plus a threshold voltage above ground or one gate overdrive plus a threshold voltage below VDD. Establishing a threshold voltage in this way enables the biasing circuit to track an ideal voltage of a varactor that is coupled to the biasing circuit through the threshold voltage.
摘要翻译：提出了一种用于产生在电容调谐应用中偏置用作变容二极管的金属氧化物半导体（MOS）晶体管的参考电压的方法和装置。在一个实施例中，实现偏置电路。偏置电路包括二极管钳位的FET和在连接点处耦合到二极管钳位的FET的元件。该元件通过二极管钳位的FET产生恒定电流。在连接点产生电压。电压是一个栅极过驱动加上高于地面的门限电压或一个栅极过驱动加上低于VDD的阈值电压。以这种方式建立阈值电压使得偏置电路能够通过阈值电压跟踪耦合到偏置电路的变容二极管的理想电压。

2. 发明申请

US20050111607A1 Phase detector system with asynchronous output override 有权
标题翻译：具有异步输出覆盖的相位检测器系统
公开(公告)号：US20050111607A1
公开(公告)日：2005-05-26
申请号：US10718206
申请日：2003-11-20
申请人： Alvin Loke , Robert Barnes , James Barnes
发明人： Alvin Loke , Robert Barnes , James Barnes
IPC分类号： H03D13/00 , H03L7/089 , H03L7/107 , H03D3/24
CPC分类号： H03D13/004 , H03L7/0891 , H03L7/107
摘要： In one embodiment, the present invention provides a phase-locked loop comprising a charge-pump loop filter and a phase detector system. The charge-pump loop filter is configured to provide a control voltage having a voltage level based on a state of a first control signal and on a state of a second control signal. The phase detector system is configured to receive a first clock, a second clock, and a control signal defining a plurality of states including a first state and a second state. The phase detector system is further configured to provide the first control signal and the second control signal each having a state based on a phase difference between the first and second clocks when the control signal has the first state, and to provide the first control signal and second control signal each having a state asynchronously controlled by the control signal when the control signal has the second state.
摘要翻译：在一个实施例中，本发明提供一种包括电荷泵环路滤波器和相位检测器系统的锁相环。电荷泵环路滤波器被配置为提供具有基于第一控制信号的状态和第二控制信号的状态的电压电平的控制电压。相位检测器系统被配置为接收限定包括第一状态和第二状态的多个状态的第一时钟，第二时钟和控制信号。相位检测器系统还被配置为当控制信号具有第一状态时，提供第一控制信号和第二控制信号，每个具有基于第一和第二时钟之间的相位差的状态，并且提供第一控制信号和当所述控制信号具有所述第二状态时，所述第二控制信号具有由所述控制信号异步控制的状态。

3. 发明申请

US20050110589A1 Self-tuning varactor system 有权
公开(公告)号：US20050110589A1
公开(公告)日：2005-05-26
申请号：US10717834
申请日：2003-11-20
申请人： Alvin Loke , Robert Barnes
发明人： Alvin Loke , Robert Barnes
IPC分类号： H03B5/00 , H03B5/12 , H03L7/07 , H03L7/099 , H03L7/18
CPC分类号： H03L7/18 , H03L7/07 , H03L7/0805 , H03L7/099 , H03L2207/06
摘要： In one embodiment, the present invention provides a system including a varactor and a voltage generator. The varactor includes a set of substantially equal voltage-tunable capacitor cells, each having a capacitive range that varies with a first plurality of operating parameters and each providing a capacitance within the range based on a voltage level of a reference voltage. The voltage generator is configured to provide the reference voltage, wherein the voltage level of the reference voltage corresponds to a desired capacitance within the capacitive range and varies based on a second plurality of operating parameters which are substantially the same as the first plurality of operating parameters, and wherein the voltage level of the reference voltage causes each capacitor cell to provide the desired capacitance.

4. 发明申请

US20050280407A1 Delay-locked loop and a method of testing a delay-locked loop 有权
标题翻译：延迟锁定环路和测试延迟锁定环路的方法
公开(公告)号：US20050280407A1
公开(公告)日：2005-12-22
申请号：US10869582
申请日：2004-06-16
申请人： Alvin Loke , Michael Joseph Gilsdorf , Peter Meier , Jeffrey R. Rearick
发明人： Alvin Loke , Michael Joseph Gilsdorf , Peter Meier , Jeffrey R. Rearick
IPC分类号： G01R23/175 , H03L7/06 , H03L7/07 , H03L7/081
CPC分类号： H03L7/07 , H03L7/0812
摘要： A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.
摘要翻译：具有测试电路的集成电路（IC）的延迟锁定环（DLL）和用于测试DLL的方法。在测试模式期间，DLL的相位比较器代替参考时钟接收测试时钟，并从时钟缓冲器树中确定测试时钟与反馈到DLL的时钟之间的相位差。然后，DLL的可变延迟元件将参考时钟在时间上移动取决于该相位差的量。可以通过将测试时钟相对于参考时钟的相位改变已知的相位偏移来使可变延迟元件产生延迟范围来实现可变延迟元件。可以通过检查测试时钟的相位是否与反馈时钟的相位对准来确定可变延迟元件是否正常工作。

5. 发明申请

US20070052511A1 Cross-coupled inductor pair formed in an integrated circuit 有权
标题翻译：交叉耦合电感对形成在集成电路中
公开(公告)号：US20070052511A1
公开(公告)日：2007-03-08
申请号：US11210989
申请日：2005-08-24
申请人： Alvin Loke , Philip Fisher , Robert Martin
发明人： Alvin Loke , Philip Fisher , Robert Martin
IPC分类号： H01F5/00
CPC分类号： H03H5/12 , H01F27/40 , H01F2017/0026 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03B5/1841 , H01L2924/00
摘要： Cross-coupled first and second helical inductors formed in an IC. The cross-coupled first and second helical inductors comprise a first helical conductor having a first portion and a second portion, and a second helical conductor having a first portion and a second portion. The second helical conductor is in close proximity to the first helical conductor. The first helical inductor is formed by the first portion of the first helical conductor and the second portion of the second helical conductor. The second helical inductor is formed by the second portion of the first helical conductor and the first portion of the second helical conductor.
摘要翻译：在IC中形成的交叉耦合的第一和第二螺旋电感器。交叉耦合的第一和第二螺旋电感器包括具有第一部分和第二部分的第一螺旋形导体和具有第一部分和第二部分的第二螺旋形导体。第二螺旋导体紧邻第一螺旋导体。第一螺旋电感器由第一螺旋导体的第一部分和第二螺旋导体的第二部分形成。第二螺旋电感器由第一螺旋导体的第二部分和第二螺旋导体的第一部分形成。

6. 发明申请

US20070052485A1 Methods and apparatuses for testing a voltage-controlled oscillator (VCO) to verify operation across supply voltage and/or temperature 失效
标题翻译：用于测试压控振荡器（VCO）以验证电源电压和/或温度之间的操作的方法和装置
公开(公告)号：US20070052485A1
公开(公告)日：2007-03-08
申请号：US11210421
申请日：2005-08-24
申请人： Alvin Loke , Michael Gilsdorf
发明人： Alvin Loke , Michael Gilsdorf
IPC分类号： H03L7/00
CPC分类号： H03L7/099
摘要： Methods and apparatuses for testing a calibrated VCO to determine whether the VCO has adequate fine frequency tuning capability. A range of coarse frequency tuning calibration settings are determined from coarse frequency tuning calibration settings obtained during a coarse frequency tuning calibration process. A determination is then made as to whether a fine frequency tuning capability of the VCO is adequate based on the determined range of coarse frequency tuning calibration settings.
摘要翻译：用于测试校准的VCO以确定VCO是否具有足够的精细频率调谐能力的方法和装置。粗频率调谐校准设置范围由粗调频调谐校准过程中获得的粗频调谐校准设置确定。然后，基于所确定的粗调频调谐校准设置的范围，确定VCO的精调频调谐能力是否足够。

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