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1. 发明授权

US06479974B2 Stacked voltage rails for low-voltage DC distribution 失效
标题翻译：用于低压直流分配的堆叠电压轨
公开(公告)号：US06479974B2
公开(公告)日：2002-11-12
申请号：US09750884
申请日：2000-12-28
申请人： John Maxwell Cohn , Alvar Antonio Dean , David James Hathaway , Patrick Edward Perry , Sebastian Theodore Ventrone
发明人： John Maxwell Cohn , Alvar Antonio Dean , David James Hathaway , Patrick Edward Perry , Sebastian Theodore Ventrone
IPC分类号： G05F304
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.
摘要翻译：一种用于提供片上电压分配和调节的系统和方法。根据本发明的系统，IC芯片包括具有用于向IC芯片供电的源极电源轨的源极电压平面和用于从其供电的电力的源极接地导轨。至少一个中间接地轨连接在源电源轨和源极接地轨之间，以将源电压平面分成多个中间电压平面。中间接地导轨用作后续中间电压平面的电源轨，使得中间电压平面串联连接。

2. 发明授权

US06477654B1 Managing VT for reduced power using power setting commands in the instruction stream 失效
标题翻译：使用指令流中的电源设置命令管理VT以降低功耗
公开(公告)号：US06477654B1
公开(公告)日：2002-11-05
申请号：US09287159
申请日：1999-04-06
申请人： Alvar Antonio Dean , Patrick Edward Perry , Sebastian Theodore Ventrone
发明人： Alvar Antonio Dean , Patrick Edward Perry , Sebastian Theodore Ventrone
IPC分类号： G06F132
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F8/4432 , G06F9/3867 , Y02D10/152 , Y02D10/171 , Y02D10/172 , Y02D10/24 , Y02D10/41
摘要： An integrated circuit includes a plurality of functional units which are capable of operating at more than one power/performance level and a power control unit. The power control unit controls the power/performance consumption of the different functional units to optimize operation of the integrated circuit. Special power control instructions are added to user applications in order to control via the power control unit, the power consumption of the different functional units.
摘要翻译：集成电路包括能够以多于一个功率/性能水平操作的多个功能单元和功率控制单元。功率控制单元控制不同功能单元的功率/性能消耗，以优化集成电路的运行。特殊功率控制指令被添加到用户应用中，以通过功率控制单元控制不同功能单元的功耗。

3. 发明授权

US06345362B1 Managing Vt for reduced power using a status table 有权
标题翻译：使用状态表管理Vt降低功耗
公开(公告)号：US06345362B1
公开(公告)日：2002-02-05
申请号：US09287173
申请日：1999-04-06
申请人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
发明人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
IPC分类号： G06F132
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F9/3867 , G06F9/3869 , Y02D10/126 , Y02D10/171
摘要： An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.
摘要翻译：集成电路包括CPU，电源管理单元和专用于执行不同功能的多个功能单元。电源管理单元控制不同功能单元的阈值电压，以优化电路的功率/性能运行，智能电源管理控制响应指令流并依次对每条指令进行解码。该信息识别特定指令需要哪个功能单元，并且通过将该信息与功率状态进行比较，智能功率控制确定执行命令所需的功能单元是否处于最佳功率级。如果是，则允许该命令继续进行，否则智能功率控制将停止指令序列或修改处理速度。

4. 发明授权

US07135907B2 Clock signal distribution utilizing differential sinusoidal signal pair 失效
公开(公告)号：US07135907B2
公开(公告)日：2006-11-14
申请号：US11255707
申请日：2005-10-21
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

5. 发明授权

US07071757B2 Clock signal distribution utilizing differential sinusoidal signal pair 有权
公开(公告)号：US07071757B2
公开(公告)日：2006-07-04
申请号：US09682473
申请日：2001-09-06
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

6. 发明授权

US06425109B1 High level automatic core configuration 有权
标题翻译：高级自动核心配置
公开(公告)号：US06425109B1
公开(公告)日：2002-07-23
申请号：US09360384
申请日：1999-07-23
申请人： Charles N. Choukalos , Alvar Antonio Dean , Scott Alan Tetreault , Sebastian Theodore Ventrone
发明人： Charles N. Choukalos , Alvar Antonio Dean , Scott Alan Tetreault , Sebastian Theodore Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.
摘要翻译：一种用于将多个核心互连成单个功能核心的系统和方法。该方法包括基于一组配置规则为每个核心创建引脚配置结构。当选择要互连的芯时，通过本发明的配置程序工具访问引脚配置结构。然后，配置程序工具使用所选核心的引脚配置结构和配置规则将内核连接在一起。配置程序工具生成互连核心的无错误高级模型。配置程序工具允许配置灵活性，并且足以处理大多数配置场景。该工具也易于编码，可扩展，并且可以应用于现有的核心设计，而不改变内核本身。

7. 发明授权

US5874833A True/complement output bus for reduced simulataneous switching noise 失效
标题翻译：用于减少模拟开关噪声的真/补输出总线
公开(公告)号：US5874833A
公开(公告)日：1999-02-23
申请号：US794041
申请日：1997-02-03
申请人： Patrick Edward Perry , Sebastian Theodore Ventrone
发明人： Patrick Edward Perry , Sebastian Theodore Ventrone
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00346
摘要： A true/complement integrated circuit device is disclosed for reducing an amount of simultaneous switching on a bus between a current state and a next state. The device includes a current state register connected to the bus for outputting the current state onto the bus during a first clock cycle. A next state register is provided for containing the next state, wherein the next state is a pending state of the bus intended for a next clock cycle. A comparison circuit compares a current state value in the current state register with a next state value in the next state register on a bit-by-bit basis to determine if the current state value and the next state value are of a same polarity or of an opposite polarity. A circuit is provided for determining a ratio of switching signals from an output of the bit-by-bit comparisons by the comparison circuit. The ratio determining circuit further generates a true/complement (T/C) signal having a first state if it is determined that more than a prescribed percentage of bits are in transition, the T/C signal having a second state otherwise. Lastly, a circuit is provided for complementing the bits of the next state register in response to the T/C signal being in the first state, and not complementing the bits of the next state register in response to the T/C signal being in the second state, prior to being transferred into the current state register and output onto the bus during the next clock cycle.
摘要翻译：公开了一种真/补体集成电路装置，用于减少在当前状态和下一状态之间的总线上的同时开关量。该装置包括连接到总线的当前状态寄存器，用于在第一时钟周期期间将当前状态输出到总线上。提供下一个状态寄存器用于包含下一个状态，其中下一个状态是下一个时钟周期的总线的待处理状态。比较电路将当前状态寄存器中的当前状态值与下一状态寄存器中的下一状态值逐位进行比较，以确定当前状态值和下一状态值是否具有相同的极性，或者相反的极性。提供了一种电路，用于确定比较电路中逐位比较输出的开关信号的比例。比例确定电路进一步产生具有第一状态的真/补（T / C）信号，如果确定多于一定比例的位正在转换，否则T / C信号具有第二状态。最后，提供一个电路来补偿下一个状态寄存器的位，以响应于T / C信号处于第一状态，并且不响应于T / C信号位于下一个状态寄存器的位第二状态，在被转移到当前状态寄存器之前，并且在下一个时钟周期内输出到总线上。

8. 发明授权

US08793365B2 Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes 有权
标题翻译：降低环境和计算成本，提高分布式计算节点工作负载分配的可靠性
公开(公告)号：US08793365B2
公开(公告)日：2014-07-29
申请号：US12397897
申请日：2009-03-04
申请人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, Jr. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
发明人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, Jr. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
IPC分类号： G06F15/173
CPC分类号： G06F9/5027 , G06F9/5094 , G06F2209/508 , Y02D10/22
摘要： A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.
摘要翻译：一种将计算任务的作业提交分配给每个具有至少一个处理实体的分布式服务器场集合的系统和方法; 从至少一个处理实体接收工作负载请求以提交给所述一组分布式服务器场中的至少一个; 使用与计算任务相关联的至少一个或多个条件来接受或拒绝要分配作业提交的至少一个服务器场; 确定可优化一个或多个条件的服务器场; 以及将所述作业提交分发到所述服务器场，所述服务器场优化与所述计算任务相关联并用于选择所述至少一个所述服务器场的所述一个或多个条件中的至少一个。

9. 发明授权

US06820254B2 Method and system for optimizing code using an optimizing coprocessor 失效
标题翻译：使用优化协处理器优化代码的方法和系统
公开(公告)号：US06820254B2
公开(公告)日：2004-11-16
申请号：US09681327
申请日：2001-03-19
申请人： Jack Robert Smith , Sebastian Theodore Ventrone
发明人： Jack Robert Smith , Sebastian Theodore Ventrone
IPC分类号： G06F945
CPC分类号： G06F8/443
摘要： A data processing system includes a central processing unit (CPU) in communication with a system memory. Within the system memory, there is stored legacy code that does not utilize the full features of the CPU. The data processing system also includes a code-optimizing coprocessor in communication with the CPU and the system memory. Control logic within the code-optimizing coprocessor causes the code-optimizing coprocessor to generate optimized code from the legacy code at the same time the CPU executes the legacy code, such that the optimized code is tailored according to the CPU. After the code-optimizing coprocessor has generated at least some optimized code, the code-optimizing coprocessor causes the CPU to automatically utilize at least some optimized code in lieu of at least some of the legacy code.
摘要翻译：数据处理系统包括与系统存储器通信的中央处理单元（CPU）。在系统内存中，存储了不利用CPU全部功能的旧版代码。数据处理系统还包括与CPU和系统存储器通信的代码优化协处理器。代码优化协处理器内的控制逻辑使得代码优化协处理器在CPU执行遗留代码的同时从旧代码生成优化的代码，使得优化的代码根据CPU进行调整。在代码优化协处理器已经生成了至少一些优化的代码之后，代码优化协处理器使CPU自动利用至少一些优化的代码来代替至少一些遗留代码。

10. 发明申请

US20090138676A1 DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS 有权
标题翻译：设计结构包括数字系统中减少噪声的电路
公开(公告)号：US20090138676A1
公开(公告)日：2009-05-28
申请号：US11946096
申请日：2007-11-28
申请人： Nancy H. Pratt , Sebastian Theodore Ventrone
发明人： Nancy H. Pratt , Sebastian Theodore Ventrone
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F1/06 , G06F1/08 , G06F9/3869
摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.
摘要翻译：包括数字系统的设计结构。数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f）一个控制器电路。第一逻辑电路能够获得第一数据并发送第二数据。第二逻辑电路能够获得第二数据并发送第三数据。时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号。控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

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