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1. 发明申请

US20100228861A1 ENVIRONMENTAL AND COMPUTING COST REDUCTION WITH IMPROVED RELIABILITY IN WORKLOAD ASSIGNMENT TO DISTRIBUTED COMPUTING NODES 有权
标题翻译：环境和计算成本降低，在分配计算节点的工作量分配中具有改进的可靠性
公开(公告)号：US20100228861A1
公开(公告)日：2010-09-09
申请号：US12397897
申请日：2009-03-04
申请人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, JR. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
发明人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, JR. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
IPC分类号： G06F9/50 , G06F9/46 , G06F15/16 , G06F15/173
CPC分类号： G06F9/5027 , G06F9/5094 , G06F2209/508 , Y02D10/22
摘要： A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.
摘要翻译：一种将计算任务的作业提交分配给每个具有至少一个处理实体的分布式服务器场集合的系统和方法; 从至少一个处理实体接收工作负载请求以提交给所述一组分布式服务器场中的至少一个; 使用与计算任务相关联的至少一个或多个条件来接受或拒绝要分配作业提交的至少一个服务器场; 确定可优化一个或多个条件的服务器场; 以及将所述作业提交分发到所述服务器场，所述服务器场优化与所述计算任务相关联并用于选择所述至少一个所述服务器场的所述一个或多个条件中的至少一个。

2. 发明授权

US08793365B2 Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes 有权
标题翻译：降低环境和计算成本，提高分布式计算节点工作负载分配的可靠性
公开(公告)号：US08793365B2
公开(公告)日：2014-07-29
申请号：US12397897
申请日：2009-03-04
申请人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, Jr. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
发明人： Igor Arsovski , Anthony Richard Bonaccio , Hayden C. Cranford, Jr. , Alfred Degbotse , Joseph Andrew Iadanza , Todd Edwin Leonard , Pradeep Thiagarajan , Sebastian Theodore Ventrone
IPC分类号： G06F15/173
CPC分类号： G06F9/5027 , G06F9/5094 , G06F2209/508 , Y02D10/22
摘要： A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.
摘要翻译：一种将计算任务的作业提交分配给每个具有至少一个处理实体的分布式服务器场集合的系统和方法; 从至少一个处理实体接收工作负载请求以提交给所述一组分布式服务器场中的至少一个; 使用与计算任务相关联的至少一个或多个条件来接受或拒绝要分配作业提交的至少一个服务器场; 确定可优化一个或多个条件的服务器场; 以及将所述作业提交分发到所述服务器场，所述服务器场优化与所述计算任务相关联并用于选择所述至少一个所述服务器场的所述一个或多个条件中的至少一个。

3. 发明授权

US07135907B2 Clock signal distribution utilizing differential sinusoidal signal pair 失效
公开(公告)号：US07135907B2
公开(公告)日：2006-11-14
申请号：US11255707
申请日：2005-10-21
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

4. 发明授权

US07071757B2 Clock signal distribution utilizing differential sinusoidal signal pair 有权
公开(公告)号：US07071757B2
公开(公告)日：2006-07-04
申请号：US09682473
申请日：2001-09-06
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

5. 发明授权

US07545297B2 Digital-to-analog converter using dual-gate transistors 失效
标题翻译：使用双栅极晶体管的数模转换器
公开(公告)号：US07545297B2
公开(公告)日：2009-06-09
申请号：US11846916
申请日：2007-08-29
申请人： Wagdi William Abadeer , Anthony Richard Bonaccio , Joseph Andrew Iadanza
发明人： Wagdi William Abadeer , Anthony Richard Bonaccio , Joseph Andrew Iadanza
IPC分类号： H03M1/00
CPC分类号： H03M1/745 , H01L29/7855
摘要： A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2n−1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.
摘要翻译：数模转换器。数模转换器包括电流镜，包括N级，每级包括2n-1个双栅极晶体管，其中N是等于或大于1的正整数，并且对于N中的每一个，n是0和N-1之间的整数阶段，n阶段的每个阶段的值不同; 一个输出，N级每级的每个双栅极晶体管连接到输出端; N个输入，N个输入的每个输入连接到N级的不同级，N个输入的任何特定输入连接到特定输入连接到的级的每个双栅极晶体管; 以及电流参考电路，包括参考电流源和参考双栅极晶体管，N级的每一级连接到电流参考电路。

6. 发明授权

US07545298B2 Design structure for a digital-to-analog converter using dual-gate transistors 失效
标题翻译：使用双栅极晶体管的数模转换器的设计结构
公开(公告)号：US07545298B2
公开(公告)日：2009-06-09
申请号：US12045055
申请日：2008-03-10
申请人： Wagdi William Abadeer , Anthony Richard Bonaccio , Joseph Andrew Iadanza
发明人： Wagdi William Abadeer , Anthony Richard Bonaccio , Joseph Andrew Iadanza
IPC分类号： H03M1/00
CPC分类号： H03M1/745 , H01L27/1203 , H01L29/785 , H01L29/7855 , H01L29/78648
摘要： A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2n−1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.
摘要翻译：体现在机器可读介质中的设计结构，该设计结构包括包括N级的电流镜，每级包括2n-1个双栅极晶体管，其中N是等于或大于1的正整数，n是0和 N-1，对于N级的每个阶段，n的值不同; 一个输出，N级每级的每个双栅极晶体管连接到输出端; N个输入，N个输入的每个输入连接到N级的不同级，N个输入的任何特定输入连接到特定输入连接到的级的每个双栅极晶体管; 以及电流参考电路，包括参考电流源和参考双栅极晶体管，N级的每一级连接到电流参考电路。

7. 发明申请

US20090058704A1 DESIGN STRUCTURE FOR A DIGITAL-TO-ANALOG CONVERTER USING DUAL-GATE TRANSISTORS 失效
标题翻译：使用双门极晶体管的数字到模拟转换器的设计结构
公开(公告)号：US20090058704A1
公开(公告)日：2009-03-05
申请号：US12045055
申请日：2008-03-10
申请人： Wagdi William Abadeer , Anthony Richard Bonaccio , Joseph Andrew Iadanza
发明人： Wagdi William Abadeer , Anthony Richard Bonaccio , Joseph Andrew Iadanza
IPC分类号： H03M1/66
CPC分类号： H03M1/745 , H01L27/1203 , H01L29/785 , H01L29/7855 , H01L29/78648
摘要： A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2n-1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.
摘要翻译：体现在机器可读介质中的设计结构，该设计结构包括包括N级的电流镜，每级包括2n-1个双栅极晶体管，其中N是等于或大于1的正整数，n是0和 N-1，对于N级的每个阶段，n的值不同; 一个输出，N级每级的每个双栅极晶体管连接到输出端; N个输入，N个输入的每个输入连接到N级的不同级，N个输入的任何特定输入连接到特定输入连接到的级的每个双栅极晶体管; 以及电流参考电路，包括参考电流源和参考双栅极晶体管，N级的每一级连接到电流参考电路。

8. 发明申请

US20090058703A1 DIGITAL-TO-ANALOG CONVERTER USING DUAL-GATE TRANSISTORS 失效
标题翻译：使用双门极晶体管的数字到模拟转换器
公开(公告)号：US20090058703A1
公开(公告)日：2009-03-05
申请号：US11846916
申请日：2007-08-29
申请人： Wagdi William Abadeer , Anthony Richard Bonaccio , Joseph Andrew Iadanza
发明人： Wagdi William Abadeer , Anthony Richard Bonaccio , Joseph Andrew Iadanza
IPC分类号： H03M1/66
CPC分类号： H03M1/745 , H01L29/7855
摘要： A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2n−1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.
摘要翻译：数模转换器。数模转换器包括电流镜，包括N级，每级包括2n-1个双栅极晶体管，其中N是等于或大于1的正整数，并且对于N中的每一个，n是0和N-1之间的整数阶段，n阶段的每个阶段的值不同; 一个输出，N级每级的每个双栅极晶体管连接到输出端; N个输入，N个输入的每个输入连接到N级的不同级，N个输入的任何特定输入连接到特定输入连接到的级的每个双栅极晶体管; 以及电流参考电路，包括参考电流源和参考双栅极晶体管，N级的每一级连接到电流参考电路。

9. 发明申请

US20080107212A1 Method for Implementing Phase Rotator Circuits and Phase Rotator Circuit With Embedded Polyphase Filter Network Stage 失效
标题翻译：实现具有嵌入式多相滤波器网络阶段的相位旋转电路和相位旋转电路的方法
公开(公告)号：US20080107212A1
公开(公告)日：2008-05-08
申请号：US11557695
申请日：2006-11-08
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , John Francis Bulzacchelli , Daniel Mark Dreps
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , John Francis Bulzacchelli , Daniel Mark Dreps
IPC分类号： H03D1/00
CPC分类号： H03H11/02
摘要： A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.
摘要翻译：用于实现本发明的相位旋转电路和相位旋转电路的方法包括多相滤波器网络，以产生输入信号的正交相位版本。多相滤波器网络被划分为与相位旋转电路物理隔离的第一部分和嵌入在相位旋转电路中的第二部分。多相滤波器的第二部分通过高通均衡缓冲级耦合到多相滤波器的第一部分。多相滤波器的第二部分通过带限幅缓冲器级耦合到相位旋转器电路。

10. 发明授权

US5859461A Method and apparatus for interfacing integrated circuits having different supply voltages 失效
标题翻译：用于连接具有不同电源电压的集成电路的方法和装置
公开(公告)号：US5859461A
公开(公告)日：1999-01-12
申请号：US829708
申请日：1997-03-28
申请人： Anthony Richard Bonaccio , Wilbur David Pricer
发明人： Anthony Richard Bonaccio , Wilbur David Pricer
IPC分类号： H03K19/0175 , H01L29/76
CPC分类号： H03K19/017509
摘要： An integrated circuit chip having circuitry to adjust its threshold voltage between a plurality of threshold voltages for interfacing to integrated circuit chips having different supply voltages. The integrated circuit chip also includes circuitry for communicating its threshold voltage level to a second integrated circuit such that the second integrated circuit may set its threshold voltage prior to receiving logic communications from the integrated circuit. The present invention also discloses an integrated circuit that detects the logic level of incoming logic communications and adjusts its threshold voltage accordingly.
摘要翻译：一种集成电路芯片，具有用于在多个阈值电压之间调整其阈值电压的电路，用于与具有不同电源电压的集成电路芯片接口。集成电路芯片还包括用于将其阈值电压电平传送到第二集成电路的电路，使得第二集成电路可以在从集成电路接收逻辑通信之前设置其阈值电压。本发明还公开了一种集成电路，其检测输入逻辑通信的逻辑电平并相应地调整其阈值电压。

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