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1. 发明授权

US07135907B2 Clock signal distribution utilizing differential sinusoidal signal pair 失效
公开(公告)号：US07135907B2
公开(公告)日：2006-11-14
申请号：US11255707
申请日：2005-10-21
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

2. 发明授权

US07071757B2 Clock signal distribution utilizing differential sinusoidal signal pair 有权
公开(公告)号：US07071757B2
公开(公告)日：2006-07-04
申请号：US09682473
申请日：2001-09-06
申请人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
发明人： Anthony Richard Bonaccio , John Maxwell Cohn , Alvar Antonio Dean , Amir H. Farrahi , David J. Hathaway , Sebastian Theodore Ventrone
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

3. 发明授权

US06711719B2 Method and apparatus for reducing power consumption in VLSI circuit designs 失效
标题翻译：用于降低VLSI电路设计中的功耗的方法和装置
公开(公告)号：US06711719B2
公开(公告)日：2004-03-23
申请号：US09928573
申请日：2001-08-13
申请人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.
摘要翻译：在集成电路（IC）设计中，功率消耗的分量可以表示为功率=½FCV <2>，其中C是由源单元驱动的负载电容，F是源单元的开关频率，V 是总输出电压摆幅。然而，不是由源单元产生的每个信号值都不需要传播到芯片的每个时钟周期连接到源的所有宿单元。因此，将隔离单元插入到将源单元连接到至少一个宿单元的网络（有线）中，以便当由所述源单元输出的信号从所述源单元输出时，将所述至少一个宿单元和所述网的一部分与所述源单元分离源不需要传播。由于去耦合，与至少一个接收器和净部分相关联的负载电容对于这种信号不被源单元体验。因此，整体IC功耗降低。

4. 发明授权

US06985004B2 Wiring optimizations for power 失效
公开(公告)号：US06985004B2
公开(公告)日：2006-01-10
申请号：US09781369
申请日：2001-02-12
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： H03K17/16
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

5. 发明授权

US07469395B2 Wiring optimizations for power 有权
标题翻译：电力接线优化
公开(公告)号：US07469395B2
公开(公告)日：2008-12-23
申请号：US11952544
申请日：2007-12-07
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.
摘要翻译：一种用于设计电气布线结构的电气布线结构和计算机系统。电气配线结构包括电线对。线对包括第一线和第二线。第二根电线被预定为三态。线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度线。

6. 发明授权

US07346875B2 Wiring optimizations for power 有权
标题翻译：电力接线优化
公开(公告)号：US07346875B2
公开(公告)日：2008-03-18
申请号：US11176712
申请日：2005-07-07
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.
摘要翻译：电气布线结构及其设计方法。该方法识别具有第一线和第二线的至少一个线对。第二根线已经是三态的，也可以是三态的。线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

7. 发明授权

US07370305B2 Method and apparatus for facilitating cell placement for an integrated circuit design 有权
标题翻译：用于促进集成电路设计的电池放置的方法和装置
公开(公告)号：US07370305B2
公开(公告)日：2008-05-06
申请号：US11350667
申请日：2006-02-08
申请人： Amir H. Farrahi , Anurag Bhatnagar , Nabanjan Das
发明人： Amir H. Farrahi , Anurag Bhatnagar , Nabanjan Das
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： One embodiment of the present invention provides a system that determines a feasible cell placement for an integrated circuit design. During operation, the system receives an input cell placement, which is typically determined using a quadratic placement technique. Next, the system receives a set of regions within the integrated circuit design. Each region has a capacity constraint which specifies an upper limit on the total cell area that can be placed within the region. The system then generates a bi-partite graph which comprises instance vertices, region vertices, and edges. An instance vertex is associated with a cell instance, a region vertex is associated with a region, and each edge is incident on an instance vertex and a region vertex. Each edge is assigned a cost that indicates the cost of placing the associated cell instance in the associated region. Next, the system associates edges with shadow edges. Note that an edge and an associated shadow edge are incident to the same instance vertex. The system then ranks the edges using the costs of the shadow edges. Next, the system selects a set of edges using the edge rankings. Finally, the system determines the feasible cell placement using the set of edges.
摘要翻译：本发明的一个实施例提供一种确定用于集成电路设计的可行单元布局的系统。在操作期间，系统接收输入单元布置，其通常使用二次放置技术来确定。接下来，系统在集成电路设计中接收一组区域。每个区域具有容量约束，其规定可以放置在该区域内的总单元格区域的上限。然后，系统生成包括实例顶点，区域顶点和边缘的双分图。实例顶点与单元格实例相关联，区域顶点与区域相关联，每个边缘都入射到实例顶点和区域顶点。为每个边缘分配一个成本，指示将关联的单元格实例放置在关联区域中的成本。接下来，系统将边缘与阴影边缘相关联。请注意，边缘和相关联的阴影边缘入射到相同的实例顶点。然后系统使用阴影边缘的成本对边缘进行排序。接下来，系统使用边缘排序来选择一组边。最后，系统使用该组边确定可行的单元布局。

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