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1. 发明授权

US6011383A Low powering apparatus for automatic reduction of power in active and standby modes 失效
标题翻译：用于在主动和待机模式下自动降低功率的低功率设备
公开(公告)号：US6011383A
公开(公告)日：2000-01-04
申请号：US120211
申请日：1998-07-21
申请人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Alvar A. Dean , Kenneth J. Goodnow , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1/32 , G05F1/110 , G06F1/00
CPC分类号： G06F1/3296 , G06F1/3203 , Y02B60/1285
摘要： A low powering apparatus for automatic reduction of power in active and standby modes is disclosed. The low powering apparatus includes a state detector, a margins of safety device and a positioning device. The state detector detects a first or second state, such as a standby state and an active state, that has predominated in a recent past. The margins of safety device indicates safe low power margins in correlation to the detected first or second state. The positioning device adjusts the power level according to the outputs of the state detector and margins of safety device. Thus, the low powering apparatus minimizes the power level of a system at the first or second state without compromising full performance of the system.
摘要翻译：公开了一种用于在主动和待机模式下自动降低功率的低功率设备。低功率装置包括状态检测器，安全装置的边缘和定位装置。状态检测器检测在最近过去占主导地位的第一或第二状态，例如待机状态和活动状态。安全装置的边缘表示与检测到的第一或第二状态相关的安全低功率余量。定位装置根据状态检测器的输出和安全装置的余量调整功率水平。因此，低功率设备使系统在第一或第二状态下的功率水平最小化，而不会影响系统的全部性能。

2. 发明授权

US06802033B1 Low-power critical error rate communications controller 失效
标题翻译：低功率关键错误率通信控制器
公开(公告)号：US06802033B1
公开(公告)日：2004-10-05
申请号：US09286855
申请日：1999-04-06
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H04L1/0053
摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要翻译：一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。

3. 发明授权

US6097241A ASIC low power activity detector to change threshold voltage 有权
标题翻译： ASIC低功率活动检测器来改变阈值电压
公开(公告)号：US6097241A
公开(公告)日：2000-08-01
申请号：US159898
申请日：1998-09-24
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1/32 , H03K3/01
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： An integrated circuit such as an ASIC device having partitioned functional units with independent threshold voltage control. A first partition is always operated in a normal mode, while subsequent partitions are maintained in a standby mode until a transition is detected at the input of the first partition. The subsequent partitions are switched to the normal mode by lowering the body voltage applied to the devices with each partition. A pulse stretcher is used to keep a partition in a normal mode for a predetermined period of time after the transition is detected.
摘要翻译：诸如具有独立阈值电压控制的具有分区功能单元的ASIC器件的集成电路。第一分区总是以正常模式操作，而后续分区保持在待机模式，直到在第一分区的输入处检测到转换。随后的分区通过降低施加到每个分区的设备的体电压而切换到正常模式。在检测到转换之后，使用脉冲展开器将分区保持在正常模式下预定的时间段。

4. 发明授权

US06532520B1 Method and apparatus for allocating data and instructions within a shared cache 失效
标题翻译：用于在共享缓存内分配数据和指令的方法和装置
公开(公告)号：US06532520B1
公开(公告)日：2003-03-11
申请号：US09394965
申请日：1999-09-10
申请人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
发明人： Alvar A. Dean , Marc R. Faucher , John W. Goetz , Kenneth J. Goodnow , Paul T. Gutwin , Stephen W. Mahin , Wilbur D. Pricer
IPC分类号： G06F1200
CPC分类号： G06F12/121 , G06F12/127 , G06F2212/1021 , G06F2212/6042
摘要： A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.
摘要翻译：提供了一种方法和装置，用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数，并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。然后，响应于检测到的预选阈值的交叉，调整统一高速缓存的替换算法，该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。替换算法优选地是LRU算法，其中调整步骤包括递增第一类型数据线的年龄指示。用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器，其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数，并且当计数器的计数超过时，在第一计数器输出上输出第一逻辑状态第一预定计数。耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态，增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。

5. 发明授权

US06604174B1 Performance based system and method for dynamic allocation of a unified multiport cache 有权
标题翻译：基于性能的系统和方法，用于动态分配统一的多端口缓存
公开(公告)号：US06604174B1
公开(公告)日：2003-08-05
申请号：US09709872
申请日：2000-11-10
申请人： Alvar A. Dean , Kenneth J. Goodnow , Stephen W. Mahin , Wilbur D. Pricer , Dana J. Thygesen , Sebastian T. Ventrone
发明人： Alvar A. Dean , Kenneth J. Goodnow , Stephen W. Mahin , Wilbur D. Pricer , Dana J. Thygesen , Sebastian T. Ventrone
IPC分类号： G06F1200
CPC分类号： G06F12/0853 , G06F12/0844 , G06F12/0846
摘要： The present invention provides a performance based system and method for dynamic allocation of a unified multiport cache. A multiport cache system is disclosed that allows multiple single-cycle look ups through a multiport tag and multiple single-cycle cache accesses from a multiport cache. Therefore, multiple processes, which could be processors, tasks, or threads can access the cache during any cycle. Moreover, the ways of the cache can be allocated to the different processes and then dynamically reallocated based on performance. Most preferably, a relational cache miss percentage is used to reallocate the ways, but other metrics may also be used.
摘要翻译：本发明提供了一种用于动态分配统一多端口高速缓存的基于性能的系统和方法。公开了一种多端口缓存系统，其允许通过多端口标签的多个单周期查找和来自多端口高速缓存的多个单周期高速缓存访问。因此，可能是处理器，任务或线程的多个进程可以在任何周期内访问高速缓存。此外，缓存的方式可以分配给不同的进程，然后基于性能动态重新分配。最优选地，使用关系高速缓存未命中百分比来重新分配方式，但也可以使用其他度量。

6. 发明授权

US06658634B1 Logic power optimization algorithm 失效
标题翻译：逻辑功率优化算法
公开(公告)号：US06658634B1
公开(公告)日：2003-12-02
申请号：US09073999
申请日：1998-05-07
申请人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.
摘要翻译：公开了一种用于消除在逻辑网络中不必要的逻辑切换的系统和方法。该方法和系统可以直接并入逻辑综合软件中，或者可以手动实现。提供了用于识别关键网络，然后在关键网络处插入网络锁存器的机制，其中每个网络锁存器由也控制相关输出锁存器的使能信号控制。每个网络锁存器包括一个电路，该电路可以在命令上保持给定逻辑节点上的最后一个逻辑电平。

7. 发明授权

US6167524A Apparatus and method for efficient battery utilization in portable personal computers 失效
标题翻译：便携式个人计算机中有效利用电池的装置和方法
公开(公告)号：US6167524A
公开(公告)日：2000-12-26
申请号：US56300
申请日：1998-04-06
申请人： Kenneth J. Goodnow , Michel S. Michail , Janak G. Patel , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Janak G. Patel , Wilbur D. Pricer , Sebastian T. Ventrone
IPC分类号： G06F1/32 , G06F9/38 , G06F1/26 , G06F1/28 , G06F1/30
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/3287 , G06F9/3836 , G06F9/3842 , G06F9/3869 , Y02D10/171
摘要： An apparatus and method controlling power consumption in portable personal computers by dynamically allocating power to the system logic. Expected total power consumption is calculated and compared to an optimum power efficiency value. The expected power consumption values for each execution unit are stored in a look-up table in actual or compressed form. If the expected total power consumption value exceeds the power efficiency value, selected execution units are made inactive. Conversely, if the power efficiency value exceeds the expected total power consumption value, execution unit functions are added in order to maintain a level current demand on the battery.
摘要翻译：一种通过动态分配系统逻辑电力来控制便携式个人计算机中的功耗的装置和方法。计算总功耗，并将其与最佳功率效率值进行比较。每个执行单元的预期功耗值以实际或压缩形式存储在查找表中。如果预期的总功耗值超过功率效率值，则使所选择的执行单元无效。相反，如果功率效率值超过预期的总功耗值，则添加执行单元功能以便保持对电池的电平电流需求。

8. 发明授权

US6081135A Device and method to reduce power consumption in integrated semiconductor devices 失效
标题翻译：集成半导体器件降低功耗的器件和方法
公开(公告)号：US6081135A
公开(公告)日：2000-06-27
申请号：US74442
申请日：1998-05-07
申请人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
IPC分类号： H03K19/00 , H03K3/033
CPC分类号： H03K19/0016
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.
摘要翻译：根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。优选实施例通过利用上拉或下拉晶体管将电路中的输入引导到在电路不活动的时段期间最小化功耗的状态来减少电路中的不需要的节点切换。通过在不活动状态下将电路输入高或低，在该电路中节点切换被减少或消除。在优选实施例中，电路的输入在与电路中最漏电晶体管的漏电流成比例的不活动时间之后全部被拉。通过定时输入拉动与泄漏电流成比例，最大限度地减少功耗，而不会由拉动本身引起的功率损耗过大。

9. 发明授权

US6111425A Very low power logic circuit family with enhanced noise immunity 有权
标题翻译：超低功耗逻辑电路系列，具有增强的抗噪声能力
公开(公告)号：US6111425A
公开(公告)日：2000-08-29
申请号：US173436
申请日：1998-10-15
申请人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K19/003 , H03K3/356 , H03K19/173 , H03K17/16
CPC分类号： H03K3/356113 , H03K19/1738
摘要： A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.
摘要翻译：一个非常低功率的逻辑电路系列，有利地提供1）保持高性能，2）显着降低的功耗，和3）增强的抗噪声能力。在第一组实施例中，使用双轨互补逻辑信号来提高对外部噪声的电路抗扰性并且减少由逻辑电路本身产生的噪声。本发明的接收机部分包括具有两个门到两个源的交叉耦合的两个输入FET。在一个优选实施例中，接收器和驱动器部分都连接在具有所有N个通道驱动器的中继器中。第二组实施例在不平衡接收机中具有单侧输入，包括到栅极N沟道的交叉耦合源极和栅极P沟道输出晶体管的交叉耦合漏极。

10. 发明授权

US06790722B1 Logic SOI structure, process and application for vertical bipolar transistor 有权
标题翻译：逻辑SOI结构，工艺和应用于垂直双极晶体管
公开(公告)号：US06790722B1
公开(公告)日：2004-09-14
申请号：US09718850
申请日：2000-11-22
申请人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
发明人： Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , Wilbur D. Pricer , William R. Tonti
IPC分类号： H01L218238
CPC分类号： H01L29/66265 , H01L21/8249 , H01L27/0623 , H01L29/7317
摘要： A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in a damascene process. The CMOS/vertical bipolar structure has the collector, base regions, and emitter regions vertically disposed on one another, the collector region having a peak dopant concentration adjacent the inter-substrate isolation oxide.
摘要翻译：用于在垂直双极晶体管中形成发射极的方法和结构包括在集电极层上提供具有集电极层和基极层的衬底，在集电极层上形成图案掩模，并在发光体材料中填充掩模中的开口大马士革过程。 CMOS /垂直双极结构具有彼此垂直设置的集电极，基极区域和发射极区域，集电极区域具有与衬底间隔离氧化物相邻的峰值掺杂剂浓度。

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