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1. 发明授权

US06603332B2 Configurable logic block for PLD with logic gate for combining output with another configurable logic block 有权
公开(公告)号：US06603332B2
公开(公告)日：2003-08-05
申请号：US10008556
申请日：2001-11-09
申请人： Alireza S. Kaviani , Sundararajarao Mohan , Ralph D. Wittig , Steven P. Young , Bernard J. New
发明人： Alireza S. Kaviani , Sundararajarao Mohan , Ralph D. Wittig , Steven P. Young , Bernard J. New
IPC分类号： H03K19177
CPC分类号： H03K19/17728
摘要： An apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The apparatus includes a CLB including a plurality of slices and a second-level logic circuit to combine the outputs of the slices. Typically, the second-level logic circuit is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of one slice with the output of another slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices. The slice may also include a dedicated function generator to increase the performance of each slice to implement wide functions, particularly sum-of-products functions. The dedicated function generator may include an AND gate and an OR gate with a multiplexer as a selector.

2. 发明授权

US07068072B2 Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit 有权
标题翻译：具有用于耦合到堆叠式第二集成电路的接口瓦的集成电路
公开(公告)号：US07068072B2
公开(公告)日：2006-06-27
申请号：US10610207
申请日：2003-06-30
申请人： Bernard J. New , Robert O. Conn , Steven P. Young , Edel M. Young
发明人： Bernard J. New , Robert O. Conn , Steven P. Young , Edel M. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2223/54473 , H01L2224/10135 , H01L2224/10165 , H01L2224/13021 , H01L2224/13099 , H01L2224/16111 , H01L2224/16147 , H01L2224/81136 , H01L2224/81141 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06565 , H01L2225/06593 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2924/19041 , H03K19/1778 , H03K19/17796
摘要： A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.
摘要翻译：第一集成电路的通用接口板包括多个微型焊盘。第二集成电路可以堆叠在第一集成电路上，使得来自第二集成电路的信号通过微型接口和接口瓦片传送到第一集成电路上的其他电路。类似地，来自第一集成电路的信号通过接口瓦片和微型接头传送到第二集成电路。在第一集成电路是具有可编程互连结构的可编程逻辑器件的情况下，接口瓦片是可编程互连结构的一部分并挂接到可编程互连结构中，并且提供用于将来自第二集成电路的信号耦合到可编程互连结构和/或用于将来自可编程互连结构的信号耦合到第二集成电路。

3. 发明授权

US06362650B1 Method and apparatus for incorporating a multiplier into an FPGA 有权
标题翻译：将乘法器并入到FPGA中的方法和装置
公开(公告)号：US06362650B1
公开(公告)日：2002-03-26
申请号：US09574714
申请日：2000-05-18
申请人： Bernard J. New , Steven P. Young
发明人： Bernard J. New , Steven P. Young
IPC分类号： H03K19177
CPC分类号： G06F15/7867 , G06F7/523 , G06F17/5054 , H03K19/17732 , H03K19/1776
摘要： One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.
摘要翻译：一列或多列多功能瓦片位于FPGA阵列的CLB瓦片之间。每个多功能瓦片包括共享路由资源的多个功能元件。在一个实施例中，多功能瓦片包括可配置的双端口RAM和共享多功能瓦片的路由资源的乘法器。 RAM包括分别耦合到第一和第二输入数据总线的第一和第二输入端口，并且分别包括耦合到第一和第二输出数据总线的第一和第二输出端口。乘法器包括耦合以从第一和第二输入数据总线接收操作数的第一和第二操作数端口，并且响应于此提供产品。在一个实施例中，使用总线复用器逻辑将产品的最高有效位（MSB）选择性地提供给第一输出数据总线，并且使用总线选择性地将产品的最低有效位（LSB）提供给第二输出数据总线多路复用逻辑

4. 发明授权

US08495122B2 Programmable device with dynamic DSP architecture 有权
标题翻译：具有动态DSP架构的可编程器件
公开(公告)号：US08495122B2
公开(公告)日：2013-07-23
申请号：US11019735
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个片包括一个模式端口，它接收模式控制信号，用于动态地改变相关片段的功能和连通性。这种改变可以在或不配置PLD的情况下发生。

5. 发明申请

US20110147949A1 HYBRID INTEGRATED CIRCUIT DEVICE 有权
标题翻译：混合集成电路设备
公开(公告)号：US20110147949A1
公开(公告)日：2011-06-23
申请号：US13038746
申请日：2011-03-02
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.
摘要翻译：描述形成混合集成电路器件的方法的实施例。该方法的该实施例包括：使用第一光刻形成第一裸片，其中第一裸片位于衬底上; 以及使用第二光刻形成第二管芯，其中所述第二管芯位于所述第一管芯上。用于形成第一裸片的第一光刻是比用于形成第二裸片的第二光刻更大的光刻。第一个模具是IO模具。

6. 发明授权

US07919845B2 Formation of a hybrid integrated circuit device 有权
标题翻译：形成混合集成电路器件
公开(公告)号：US07919845B2
公开(公告)日：2011-04-05
申请号：US12004906
申请日：2007-12-20
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H01L23/02
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.
摘要翻译：描述了混合集成电路器件的形成。获得集成电路的设计并将其分离成响应于部件尺寸的至少两个部分。使用至少部分第一最小尺寸光刻形成用于混合集成电路器件的第一部分的第一裸片。使用至少部分第二最小尺寸光刻形成用于装置的第二部分的第二模具，其中第二模具具有作为用于形成第二模具的最小光刻的第二最小尺寸光刻。第一管芯和第二管芯分别通过其耦合互连件彼此附接以提供混合集成电路器件。

7. 发明申请

US20090160482A1 Formation of a hybrid integrated circuit device 有权
标题翻译：形成混合集成电路器件
公开(公告)号：US20090160482A1
公开(公告)日：2009-06-25
申请号：US12004906
申请日：2007-12-20
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H03K19/177 , G06F17/50 , H01L23/48 , H01L21/58
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).
摘要翻译：描述了混合集成电路器件（400）的形成。获得集成电路（100）的设计，并将其分离成响应于部件尺寸的至少两个部分。使用至少部分第一最小尺寸光刻法，为混合集成电路器件（400）的第一部分形成第一裸片（200）。使用至少部分第二最小尺寸光刻形成用于装置的第二部分的第二裸片（300），其中第二裸片（300）具有作为用于形成第二裸片的最小光刻的第二最小尺寸光刻死（300）。第一管芯（200）和第二管芯（300）分别通过其连接互连件彼此附接以提供混合集成电路器件（400）。

8. 发明授权

US07472155B2 Programmable logic device with cascading DSP slices 有权
标题翻译：具有级联DSP片的可编程逻辑器件
公开(公告)号：US07472155B2
公开(公告)日：2008-12-30
申请号：US11019783
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , G06F15/7867 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个DSP片包括多个操作数输入端口和片输出端口，所有这些端口都可编程地连接到通用路由和逻辑资源。操作数端口接收处理的操作数，切片输出端口传送处理结果。每个切片还包括连接到相应切片输出端口的反馈端口，以支持在该实施例中的累积功能，以及连接到上游切片的输出端口以支持级联的级联输入端口。

9. 发明授权

US07467175B2 Programmable logic device with pipelined DSP slices 有权
标题翻译：可编程逻辑器件，带流水线DSP片
公开(公告)号：US07467175B2
公开(公告)日：2008-12-16
申请号：US11019782
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以组合的DSP片段，以创建不同大小和复杂度的DSP电路。根据一些实施例的DSP片段包括可被配置为从零到两个时钟周期引入不同量的延迟的可编程操作数输入寄存器，例如以支持流水线化。在一个这样的实施例中，每个DSP片包括具有乘法器端口，被乘数端口和产品端口的部分乘积生成器。乘法器和被乘数端口通过相应的第一和第二操作数输入寄存器连接到操作数输入端口，每个第一和第二操作数输入寄存器能够从零延迟到两个延迟的时钟周期。在另一个实施例中，至少一个操作数输入寄存器的输出可以连接到下游DSP片的操作数输入寄存器的输入，使得操作数可以在一个或多个片之间传送。

10. 发明授权

US06573749B2 Method and apparatus for incorporating a multiplier into an FPGA 有权
公开(公告)号：US06573749B2
公开(公告)日：2003-06-03
申请号：US10043958
申请日：2002-01-08
申请人： Bernard J. New , Steven P. Young
发明人： Bernard J. New , Steven P. Young
IPC分类号： H03K19177
CPC分类号： G06F15/7867 , G06F7/523 , G06F17/5054 , H03K19/17732 , H03K19/1776
摘要： One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

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