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1. 发明授权

US08293547B2 Hybrid integrated circuit device 有权
标题翻译：混合集成电路器件
公开(公告)号：US08293547B2
公开(公告)日：2012-10-23
申请号：US13038746
申请日：2011-03-02
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H01L21/00
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.
摘要翻译：描述形成混合集成电路器件的方法的实施例。该方法的该实施例包括：使用第一光刻形成第一裸片，其中第一裸片位于衬底上; 以及使用第二光刻形成第二管芯，其中所述第二管芯位于所述第一管芯上。用于形成第一裸片的第一光刻是比用于形成第二裸片的第二光刻更大的光刻。第一个模具是IO模具。

2. 发明申请

US20110147949A1 HYBRID INTEGRATED CIRCUIT DEVICE 有权
标题翻译：混合集成电路设备
公开(公告)号：US20110147949A1
公开(公告)日：2011-06-23
申请号：US13038746
申请日：2011-03-02
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.
摘要翻译：描述形成混合集成电路器件的方法的实施例。该方法的该实施例包括：使用第一光刻形成第一裸片，其中第一裸片位于衬底上; 以及使用第二光刻形成第二管芯，其中所述第二管芯位于所述第一管芯上。用于形成第一裸片的第一光刻是比用于形成第二裸片的第二光刻更大的光刻。第一个模具是IO模具。

3. 发明授权

US07919845B2 Formation of a hybrid integrated circuit device 有权
标题翻译：形成混合集成电路器件
公开(公告)号：US07919845B2
公开(公告)日：2011-04-05
申请号：US12004906
申请日：2007-12-20
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H01L23/02
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.
摘要翻译：描述了混合集成电路器件的形成。获得集成电路的设计并将其分离成响应于部件尺寸的至少两个部分。使用至少部分第一最小尺寸光刻形成用于混合集成电路器件的第一部分的第一裸片。使用至少部分第二最小尺寸光刻形成用于装置的第二部分的第二模具，其中第二模具具有作为用于形成第二模具的最小光刻的第二最小尺寸光刻。第一管芯和第二管芯分别通过其耦合互连件彼此附接以提供混合集成电路器件。

4. 发明申请

US20090160482A1 Formation of a hybrid integrated circuit device 有权
标题翻译：形成混合集成电路器件
公开(公告)号：US20090160482A1
公开(公告)日：2009-06-25
申请号：US12004906
申请日：2007-12-20
申请人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
发明人： James Karp , Steven P. Young , Bernard J. New , Scott S. Nance , Patrick J. Crotty
IPC分类号： H03K19/177 , G06F17/50 , H01L23/48 , H01L21/58
CPC分类号： H03K19/177 , G06F17/5068 , H01L24/48 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/19041 , H01L2924/37001 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).
摘要翻译：描述了混合集成电路器件（400）的形成。获得集成电路（100）的设计，并将其分离成响应于部件尺寸的至少两个部分。使用至少部分第一最小尺寸光刻法，为混合集成电路器件（400）的第一部分形成第一裸片（200）。使用至少部分第二最小尺寸光刻形成用于装置的第二部分的第二裸片（300），其中第二裸片（300）具有作为用于形成第二裸片的最小光刻的第二最小尺寸光刻死（300）。第一管芯（200）和第二管芯（300）分别通过其连接互连件彼此附接以提供混合集成电路器件（400）。

5. 发明授权

US5933025A Low voltage interface circuit with a high voltage tolerance 失效
标题翻译：具有高电压容差的低压接口电路
公开(公告)号：US5933025A
公开(公告)日：1999-08-03
申请号：US784163
申请日：1997-01-15
申请人： Scott S. Nance , Mohammad R. Tamjidi , Richard C. Li , Jennifer Wong , Hassan K. Bazargan
发明人： Scott S. Nance , Mohammad R. Tamjidi , Richard C. Li , Jennifer Wong , Hassan K. Bazargan
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/09429 , H03K19/00315 , H03K19/018521
摘要： A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin. In high impedance mode when the externally applied voltage at the I/O pin is sufficiently below the interface circuit supply voltage, the isolation circuit is driven to approximately the interface circuit supply voltage. In low impedance mode the isolation circuitry is disabled and the logic level at the data terminal is transmitted to the I/O pin. One embodiment of the present invention provides a buffered data path from the data terminal to the I/O pin.
摘要翻译：具有高电压公差的低压接口电路使得具有不同电源电平的器件能够有效耦合在一起，而不会有明显的漏电流或电路损坏。本发明的一个实施例包括三态控制电路，数据通路，参考电压电路和隔离电路。接口电路提供高阻抗接收模式。在这种模式下，当接口电路的I / O引脚施加的电压足够大于接口电路电源电压时，隔离电路会将电源与I / O引脚隔离开来。接口电路还保护所有的晶体管从栅极到体积，栅极到源极和漏极到大于指定电压的电压降，例如对于额定3V电源的3.6V，当高达5.5V被外部施加到 I / O引脚。在高阻抗模式下，当I / O引脚的外部施加电压足够低于接口电路电源电压时，隔离电路被驱动到大致接口电路电源电压。在低阻模式下，隔离电路被禁用，数据端子的逻辑电平被传输到I / O引脚。本发明的一个实施例提供从数据终端到I / O引脚的缓冲数据路径。

6. 发明授权

US5715197A Multiport RAM with programmable data port configuration 失效
标题翻译：多端口RAM，具有可编程数据端口配置
公开(公告)号：US5715197A
公开(公告)日：1998-02-03
申请号：US687902
申请日：1996-07-29
申请人： Scott S. Nance , Douglas P. Sheppard , Nicholas J. Sawyer
发明人： Scott S. Nance , Douglas P. Sheppard , Nicholas J. Sawyer
IPC分类号： G11C7/10 , G11C13/00
CPC分类号： G11C7/1006
摘要： A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array to implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word. The decoder receives configuration programming bits to determine the appropriate size of the RAM input and output word for the respective port, and based on column addressing bits, outputs a select signal to select the appropriate mapping from the input and output multiplexers. Decoding circuitry is used during RAM write operations to disable those input bits not addressed.
摘要翻译：具有可编程数据端口配置的RAM提供RAM数据端口的可编程配置，并且在多端口RAM的情况下，用于每个数据端口的独立可编程配置。可以在各种数据端口配置中使用单个可编程RAM单元，从而减少标准单元库或门阵列中所需的组合的数量，以实现每个可能的配置。在本发明的一个实施例中，双端口RAM提供有解码器，输入多路复用器和用于每个数据端口的输出多路复用器。每个数据端口的输入多路复用器提供与各个数据端口的输入位线不同大小的RAM输入字的几种不同的可选择的映射。类似地，每个数据端口的输出多路复用器提供RAM输出位线到RAM输出字的几种不同的可选择的映射。解码器接收配置编程位以确定相应端口的RAM输入和输出字的适当大小，并且基于列寻址位，输出选择信号以从输入和输出多路复用器选择适当的映射。在RAM写操作期间使用解码电路来禁用未寻址的输入位。

7. 再颁专利

USRE40423E1 Multiport RAM with programmable data port configuration 有权
标题翻译：多端口RAM，具有可编程数据端口配置
公开(公告)号：USRE40423E1
公开(公告)日：2008-07-08
申请号：US09858635
申请日：2001-05-15
申请人： Scott S. Nance , Douglas P. Sheppard , Nicholas J. Sawyer
发明人： Scott S. Nance , Douglas P. Sheppard , Nicholas J. Sawyer
IPC分类号： G11C16/04
CPC分类号： G11C7/1006
摘要： A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array in implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word. The decoder receives configuration programming bits to determine the appropriate size of the RAM input and output word for the respective port, and based on column addressing bits, outputs a select signal to select the appropriate mapping from the input and output multiplexers. Decoding circuitry is used during RAM write operations to disable those input bits not addressed.
摘要翻译：具有可编程数据端口配置的RAM提供RAM数据端口的可编程配置，并且在多端口RAM的情况下，用于每个数据端口的独立可编程配置。单个可编程RAM单元可以用于各种数据端口配置，从而减少标准单元库或门阵列中实现所有可能配置所需组合的数量。在本发明的一个实施例中，双端口RAM提供有解码器，输入多路复用器和用于每个数据端口的输出多路复用器。每个数据端口的输入多路复用器提供与各个数据端口的输入位线不同大小的RAM输入字的几种不同的可选择的映射。类似地，每个数据端口的输出多路复用器提供RAM输出位线到RAM输出字的几种不同的可选择的映射。解码器接收配置编程位以确定相应端口的RAM输入和输出字的适当大小，并且基于列寻址位，输出选择信号以从输入和输出多路复用器选择适当的映射。在RAM写操作期间使用解码电路来禁用未寻址的输入位。

8. 发明授权

US5877979A Single-sided RAM cell and method of accessing same 失效
标题翻译：单面RAM单元及其访问方式
公开(公告)号：US5877979A
公开(公告)日：1999-03-02
申请号：US884369
申请日：1997-06-26
申请人： Richard C. Li , Hy V. Nguyen , Scott S. Nance
发明人： Richard C. Li , Hy V. Nguyen , Scott S. Nance
IPC分类号： G11C11/412 , G11C11/00
CPC分类号： G11C11/412
摘要： A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell. Because the first voltage supply terminal is used to write both the first and second data values to the memory cell, problems associated with inadequate write voltages are eliminated by appropriate selection of the first supply voltage.
摘要翻译：提供具有单面存储单元，第一电压供应端子和控制电路的存储器系统。单面存储单元具有第一节点和第二节点。通过选择性地将数据信号应用于第一节点或第二节点，将数据值写入存储器单元，并且从第二节点从存储器单元读取数据值。控制电路被耦合以接收具有第一状态和第二状态之一的数据信号。当数据信号处于第一状态时，控制电路将存储单元的第一节点耦合到第一电压提供端，从而将第一数据值写入存储单元。当数据信号处于第二状态时，控制电路将存储单元的第二节点耦合到第一电压供应端，从而将第二数据值写入存储单元。因为第一电压供应端用于将第一和第二数据值写入存储单元，所以通过适当地选择第一电源电压来消除与写入电压不足有关的问题。

9. 发明授权

US6028450A Programmable input/output circuit with pull-up bias control 失效
标题翻译：具有上拉偏置控制的可编程输入/输出电路
公开(公告)号：US6028450A
公开(公告)日：2000-02-22
申请号：US40497
申请日：1998-03-17
申请人： Scott S. Nance
发明人： Scott S. Nance
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315
摘要： A programmable input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal, the I/O circuit including a pull-up transistor, a gate bias control circuit and a well bias control circuit, all being connected between Vcc and the I/O terminal. The gate bias control circuit connects the gate of the pull-up transistor to the I/O terminal and the well bias control circuit connects the bulk terminal of the pull-up transistor to the I/O terminal when the I/O circuit is in a 5V tolerant input mode. The gate bias control circuit connects the gate of the pull-up transistor to the system voltage source and the well bias control circuit connects the bulk terminal of the pull-up transistor to Vcc when the I/O circuit is in a PCI compliant input mode. In an output mode, the gate bias control circuit and well bias control circuit allow the pull-up transistor to pull up the I/O terminal to Vcc in response to a pull-up data signal.
摘要翻译：一种用于在I / O端子上传输输入信号或从I / O端子接收输入信号的可编程输入/输出（I / O）电路，所述I / O电路包括上拉晶体管，栅极偏置控制电路和阱偏置控制电路，全部连接在Vcc和I / O端子之间。栅极偏置控制电路将上拉晶体管的栅极连接到I / O端子，并且当I / O电路处于时，阱偏置控制电路将上拉晶体管的体端连接到I / O端子 5V容限输入模式。栅极偏置控制电路将上拉晶体管的栅极连接到系统电压源，并且当I / O电路处于PCI兼容输入模式时，阱偏置控制电路将上拉晶体管的体端连接到Vcc 。在输出模式中，栅极偏置控制电路和阱偏置控制电路允许上拉晶体管响应于上拉数据信号将I / O端子上拉至Vcc。

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