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1. 发明申请

US20140035560A1 METHOD AND APPARATUS FOR LIMITING ACCESS TO AN INTEGRATED CIRCUIT (IC) 有权
标题翻译：限制访问集成电路（IC）的方法和装置
公开(公告)号：US20140035560A1
公开(公告)日：2014-02-06
申请号：US13566363
申请日：2012-08-03
申请人： Alfredo Olmos , James R. Feddeler , Miten H. Nagda , Stefano Pietri
发明人： Alfredo Olmos , James R. Feddeler , Miten H. Nagda , Stefano Pietri
IPC分类号： G01R23/14
CPC分类号： G06F21/81 , G01R31/31719 , G06F1/14 , G06F1/28
摘要： A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
摘要翻译：提供了一种在检测到异常状况时限制对集成电路（IC）的访问的方法和装置。以低功耗提供异常电压检测，异常温度检测和异常时钟检测中的至少一种。可以检测异常低和异常高的参数值（例如异常低或高电压，温度或时钟频率）。异常时钟检测还可以检测停止的时钟信号，包括以低逻辑电平或高逻辑电平停止的时钟信号。此外，异常时钟检测可以检测时钟信号的异常占空比。采样的带隙基准可用于提供精确的电压和电流参考，同时消耗最小的功率。在检测到异常参数值时，可以提供一个或多个篡改指示以启动篡改对策，例如限制对IC的访问。

2. 发明授权

US09046570B2 Method and apparatus for limiting access to an integrated circuit (IC) 有权
标题翻译：用于限制对集成电路（IC）的访问的方法和装置
公开(公告)号：US09046570B2
公开(公告)日：2015-06-02
申请号：US13566363
申请日：2012-08-03
申请人： Alfredo Olmos , James R. Feddeler , Miten H. Nagda , Stefano Pietri
发明人： Alfredo Olmos , James R. Feddeler , Miten H. Nagda , Stefano Pietri
IPC分类号： G01R23/14 , G01R31/317
CPC分类号： G06F21/81 , G01R31/31719 , G06F1/14 , G06F1/28
摘要： A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
摘要翻译：提供了一种在检测到异常状况时限制对集成电路（IC）的访问的方法和装置。以低功耗提供异常电压检测，异常温度检测和异常时钟检测中的至少一种。可以检测异常低和异常高的参数值（例如异常低或高电压，温度或时钟频率）。异常时钟检测还可以检测停止的时钟信号，包括以低逻辑电平或高逻辑电平停止的时钟信号。此外，异常时钟检测可以检测时钟信号的异常占空比。采样的带隙基准可用于提供精确的电压和电流参考，同时消耗最小的功率。当检测到异常参数值时，可以提供一个或多个篡改指示以启动篡改对策，例如限制对IC的访问。

3. 发明授权

US09197231B1 Systems and methods for data conversion 有权
标题翻译：用于数据转换的系统和方法
公开(公告)号：US09197231B1
公开(公告)日：2015-11-24
申请号：US14266193
申请日：2014-04-30
申请人： James R. Feddeler , Michael T. Berens
发明人： James R. Feddeler , Michael T. Berens
IPC分类号： H03M1/12 , H03M1/06 , H03M1/38 , H03M1/40 , H03M1/46
CPC分类号： H03M1/468 , H03M1/0639 , H03M1/0675 , H03M1/069 , H03M1/12 , H03M1/38 , H03M1/40 , H03M1/403 , H03M1/46
摘要： Systems and methods for electronically converting an analog signal to a digital signal are disclosed. The systems and methods may include, for a first bit value, setting a first conversion value to include a first offset; using the output of a first comparison, setting a second conversion value; and if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value, and, using the output of a second comparison, setting a third conversion value.
摘要翻译：公开了将模拟信号电转换为数字信号的系统和方法。对于第一位值，系统和方法可以包括设置第一转换值以包括第一偏移量; 使用第一比较的输出，设置第二转换值; 并且如果所述第一比特值与所述第一偏移比特值具有预定关系，则从所述第二转换值中移除所述第一偏移量，并且使用所述第二比较的输出来设置第三转换值。

4. 发明授权

US08477052B2 Method and apparatus for self-test of successive approximation register (SAR) A/D converter 有权
公开(公告)号：US08477052B2
公开(公告)日：2013-07-02
申请号：US13079818
申请日：2011-04-05
申请人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
发明人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

5. 发明申请

US20120256774A1 METHOD AND APPARATUS FOR SELF-TEST OF SUCCESSIVE APPROXIMATION REGISTER (SAR) A/D CONVERTER 有权
标题翻译：自适应寄存器（SAR）A / D转换器自检的方法和装置
公开(公告)号：US20120256774A1
公开(公告)日：2012-10-11
申请号：US13079818
申请日：2011-04-05
申请人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
发明人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
摘要翻译：单端SAR ADC包括一个额外的电容器，一个自检引擎，以及对采样和保持条件的独立控制，可以对ADC进行快速准确的测试。

6. 发明申请

US20100079325A1 DATA CONVERSION CIRCUITRY AND METHOD THEREFOR 有权
公开(公告)号：US20100079325A1
公开(公告)日：2010-04-01
申请号：US12242077
申请日：2008-09-30
申请人： Michael T. Berens , James R. Feddeler
发明人： Michael T. Berens , James R. Feddeler
IPC分类号： G01B11/00
CPC分类号： H03M1/007 , H03M1/1038 , H03M1/46 , H03M1/468 , H03M1/804 , H03M1/808
摘要： A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

7. 发明授权

US5546588A Method and apparatus for preventing a data processing system from entering a non-recoverable state 失效
标题翻译：防止数据处理系统进入不可恢复状态的方法和装置
公开(公告)号：US5546588A
公开(公告)日：1996-08-13
申请号：US350396
申请日：1994-12-05
申请人： Vincent B. Deems , Gregory A. Racino , James R. Feddeler , Victor E. Shiff
发明人： Vincent B. Deems , Gregory A. Racino , James R. Feddeler , Victor E. Shiff
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/30083
摘要： A method and apparatus for preventing a data processing system (10) from entering a non-recoverable state. In one form, the present invention uses a pin (40) to indicate whether or not the execution of a non-recoverable instruction is legal. If the pin indicates that the execution of the instruction is legal, then the instruction is executed and the data processing system (10) is placed into a state that requires an external stimulus in order to recover. If the pin indicates that the execution of the instruction is illegal, then the instruction is not permitted to place the data processing system (10) into a state that requires an external stimulus in order to recover. Instead, an internal recovery mechanism is provided which returns the data processing system (10) to normal processing.
摘要翻译：一种用于防止数据处理系统（10）进入不可恢复状态的方法和装置。在一种形式中，本发明使用销（40）来指示不可恢复指令的执行是否合法。如果引脚指示指令的执行是合法的，则执行指令，并且数据处理系统（10）被置于需要外部刺激以恢复的状态。如果引脚指示执行指令是非法的，则不允许指令将数据处理系统（10）置于需要外部刺激的状态以便恢复。而是提供一种将数据处理系统（10）返回到正常处理的内部恢复机制。

8. 发明申请

US20130249723A1 METHOD AND APPARATUS FOR SELF-TEST OF SUCCESSIVE APPROXIMATION REGISTER (SAR) A/D CONVERTER 有权
标题翻译：自适应寄存器（SAR）A / D转换器自检的方法和装置
公开(公告)号：US20130249723A1
公开(公告)日：2013-09-26
申请号：US13901590
申请日：2013-05-24
申请人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
发明人： Sanjoy K. Dey , Michael T. Berens , James R. Feddeler , Vikram Varma
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/109 , H03M1/468
摘要： A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
摘要翻译：单端SAR ADC包括一个额外的电容器，一个自检引擎，以及对采样和保持条件的独立控制，可以对ADC进行快速准确的测试。

9. 发明申请

US20100320997A1 METHOD AND CIRCUIT FOR MEASURING QUIESCENT CURRENT 有权
标题翻译：用于测量电流的方法和电路
公开(公告)号：US20100320997A1
公开(公告)日：2010-12-23
申请号：US12487798
申请日：2009-06-19
申请人： Dale J. McQuirk , Michael T. Berens , James R. Feddeler
发明人： Dale J. McQuirk , Michael T. Berens , James R. Feddeler
IPC分类号： G01R19/00
CPC分类号： G01R31/3008
摘要： A measurement circuit and method for measuring a quiescent current of a circuit under test are provided. The measurement circuit comprises: a comparator having a first input terminal for receiving a reference voltage, a second input terminal coupled to the circuit under test, and an output terminal; a current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal for providing a current to the circuit under test; a first switch having a first terminal coupled to the second terminal of the current source, a second terminal coupled to the circuit under test, and a control terminal coupled to the output terminal of the comparator; and a first counter having a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving a clock signal, and an output terminal for providing a first counter value associated with the quiescent current.
摘要翻译：提供了一种用于测量被测电路的静态电流的测量电路和方法。测量电路包括：比较器，具有用于接收参考电压的第一输入端子，耦合到被测电路的第二输入端子和输出端子; 具有耦合到第一电源电压端子的第一端子的电流源和用于向被测电路提供电流的第二端子; 第一开关，其具有耦合到电流源的第二端子的第一端子，耦合到被测电路的第二端子和耦合到比较器的输出端子的控制端子; 以及第一计数器，具有耦合到比较器的输出端的第一输入端，用于接收时钟信号的第二输入端，以及用于提供与静态电流相关联的第一计数值的输出端。

10. 发明申请

US20100079319A1 DATA CONVERSION CIRCUITRY AND METHOD THEREFOR 有权
公开(公告)号：US20100079319A1
公开(公告)日：2010-04-01
申请号：US12242124
申请日：2008-09-30
申请人： Michael T. Berens , James R. Feddeler
发明人： Michael T. Berens , James R. Feddeler
IPC分类号： H03M1/10
CPC分类号： H03M1/1038 , H03M1/468 , H03M1/68 , H03M1/804
摘要： A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

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