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1. 发明申请

US20110114597A1 BARRIER INTEGRATION SCHEME FOR HIGH-RELIABILITY VIAS 审中-公开
标题翻译：用于高可靠性VIAS的障碍整合方案
公开(公告)号：US20110114597A1
公开(公告)日：2011-05-19
申请号：US12834598
申请日：2010-07-12
申请人： Alfred J. Griffin, JR. , Edmund Burke , Asad M. Haider , Kelly J. Taylor , Tae S. Kim
发明人： Alfred J. Griffin, JR. , Edmund Burke , Asad M. Haider , Kelly J. Taylor , Tae S. Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/2855 , H01L21/32131 , H01L21/76805 , H01L21/76829 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76867 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.
摘要翻译：公开了一种制造集成电路的方法，包括图案化介电层以形成具有侧壁和底部的孔。孔可以暴露导电材料的下层材料。该方法还包括将侧壁和暴露的下层材料暴露于等离子体蚀刻，在等离子体蚀刻清洁之后，在孔的底部和侧壁上沉积阻挡层，在下面的材料中通过蚀刻通过在孔的底部的阻挡层进入下面的导电金属，将阻挡材料的薄层快速沉积到孔中，最后在覆盖包括锥体的孔的侧壁和底部的孔中沉积金属种子层底端。最后通过在孔中沉积金属层来填充孔。

2. 发明授权

US07332425B2 Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects 有权
标题翻译：用于微电子器件互连中阻挡层形成的同时沉积和蚀刻工艺
公开(公告)号：US07332425B2
公开(公告)日：2008-02-19
申请号：US11126460
申请日：2005-05-11
申请人： Asad M. Haider , Alfred J. Griffin, Jr. , Kelly J. Taylor
发明人： Asad M. Haider , Alfred J. Griffin, Jr. , Kelly J. Taylor
IPC分类号： H01L21/4763
CPC分类号： H01L21/76865 , Y10S438/905
摘要： The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 110. RF plasma etching of the barrier material 200 that is deposited in the opening 140 occurs simultaneously with conducting the physical vapor deposition of the barrier material 200.
摘要翻译：本发明提供一种形成互连阻挡层100的方法。在该方法中，阻挡材料200的物理气相沉积在位于衬底110的电介质层135中的开口140内进行。沉积在开口140中的阻挡材料200的RF等离子体蚀刻与导电阻挡材料200的物理气相沉积同时发生。

3. 发明授权

US06069095A Ultra-clean wafer chuck assembly for moisture-sensitive processes conducted in rapid thermal processors 有权
标题翻译：用于在快速热处理器中进行湿敏工艺的超清洁晶片卡盘组件
公开(公告)号：US06069095A
公开(公告)日：2000-05-30
申请号：US137853
申请日：1998-08-21
申请人： Asad M. Haider
发明人： Asad M. Haider
IPC分类号： H01L21/00 , H01L21/26 , H01L21/336 , H01L21/44
CPC分类号： H01L21/67115
摘要： A method of thermal processing of semiconductor wafers during device fabrication wherein there is provided a processing chamber for thermal processing of a semiconductor wafer having a component-containing surface and an opposing backside. A retainer is provided for retaining the wafer within the chamber whereby the wafer, when retained by the retainer, forms an enclosed space in the chamber with the backside. A wafer is retained in the chamber with the retainer and the wafer is heated. Concurrent with the heating of the wafer, the fluid content of the enclosed space is continually removed while the wafer is in the processing chamber. The fluid content of the space which was the enclosed space is continually removed while the wafer is removed from the chamber after completion of the heating cycle thereon. The continual removal of fluid content can comprise purging the enclosed space with a moving gas inert to the materials in the chamber or the application of a vacuum to the enclosed space. The vacuum can be formed by providing a Venturi. A gas inert to the materials in the chamber is also passed over the component-containing surface.
摘要翻译：一种在器件制造期间半导体晶片的热处理方法，其中提供了用于具有含元件表面和相对背面的半导体晶片的热处理的处理室。提供保持器用于将晶片保持在室内，由此当由保持器保持时晶片在具有背面的腔室中形成封闭空间。晶片通过保持器保持在腔室中，并且晶片被加热。与晶片的加热同时，当晶片处于处理室中时，封闭空间的流体含量被连续地移除。在完成加热循环之后将晶片从腔室中取出时，连续地除去作为封闭空间的空间的流体含量。持续去除流体内容物可以包括用对室中的材料惰性的移动气体或向封闭空间施加真空来清洗封闭空间。可以通过提供文丘里管来形成真空。对室中的材料惰性的气体也通过含元件的表面。

4. 发明授权

US07144802B2 Vapor deposition of benzotriazole (BTA) for protecting copper interconnects 有权
公开(公告)号：US07144802B2
公开(公告)日：2006-12-05
申请号：US10405590
申请日：2003-04-01
申请人： ChangFeng F. Xia , Arunthathi Sivasothy , Ricky A. Jackson , Asad M. Haider
发明人： ChangFeng F. Xia , Arunthathi Sivasothy , Ricky A. Jackson , Asad M. Haider
IPC分类号： H01L21/4763
CPC分类号： C23C14/12 , H01L21/76838
摘要： A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.

5. 发明授权

US06803641B2 MIM capacitors and methods for fabricating same 有权
标题翻译： MIM电容器及其制造方法
公开(公告)号：US06803641B2
公开(公告)日：2004-10-12
申请号：US10638596
申请日：2003-08-11
申请人： Satyavolu S. Papa Rao , Asad M. Haider , Kelly Taylor , Ed Burke
发明人： Satyavolu S. Papa Rao , Asad M. Haider , Kelly Taylor , Ed Burke
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L27/0805 , Y10T29/417
摘要： Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.
摘要翻译：描述了用于制造其的半导体器件及其制造方法，其中使用单个高k或铁电介质层来形成去耦电容器和模拟电容器段。模拟电容器通过将模拟电容器段彼此串联耦合而形成，其中电容器段可以以相反的极性关系连接，从而为模拟电容器提供对称的性能特性。

6. 发明授权

US08907446B2 Integrated circuit structure with capacitor and resistor and method for forming 有权
标题翻译：具有电容器和电阻器的集成电路结构及其形成方法
公开(公告)号：US08907446B2
公开(公告)日：2014-12-09
申请号：US12783044
申请日：2010-05-19
申请人： Scott R. Summerfelt , Byron L. Williams , Scott K. Montgomery , James Klawinsky , Asad M. Haider
发明人： Scott R. Summerfelt , Byron L. Williams , Scott K. Montgomery , James Klawinsky , Asad M. Haider
IPC分类号： H01L29/00 , H01L49/02 , H01L23/522 , H01L27/01
CPC分类号： H01L28/40 , H01L23/5223 , H01L23/5228 , H01L27/016 , H01L28/20 , H01L28/24 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.
摘要翻译：具有金属对金属电容器的集成电路结构和电容器，阴极或局部互连的金属器件，其中电容器的底板和金属器件形成有相同的材料层。用于与金属对金属电容器一起形成金属器件的方法，而不需要额外的制造步骤。

7. 发明授权

US07960840B2 Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level 有权
标题翻译：双晶片载体工艺，用于创建具有通过硅通孔和微电子机械系统的集成电路裸片，该芯片由在晶片级产生的密封腔保护
公开(公告)号：US07960840B2
公开(公告)日：2011-06-14
申请号：US12463830
申请日：2009-05-11
申请人： Thomas Dyer Bonifield , Thomas W. Winter , William R. Morrison , Gregory D. Winterton , Asad M. Haider
发明人： Thomas Dyer Bonifield , Thomas W. Winter , William R. Morrison , Gregory D. Winterton , Asad M. Haider
IPC分类号： H01L23/52
CPC分类号： B81C1/0023 , B81B2207/096 , B81C2201/0191 , H01L21/6835 , H01L21/76898 , H01L2924/14
摘要： A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side of the product wafer to expose TSV tips, detaching the first carrier from the front side of the product wafer, and transferring the thinned wafer to a second carrier with back side adhered to the second wafer carrier. Semiconductor components are added to the front side of the product wafer, followed by forming a hermetic cavity over the added semiconductor components, and detaching the second carrier from the back side of the product wafer. Wafer level processing continues after detaching the second carrier.
摘要翻译：提供TSV-MEMS封装工艺。该方法包括在形成TSV之后，在产品晶片的前侧形成TSV，并将第一载体附接到产品晶片的前侧。该方法还包括使产品晶片的背面变薄以暴露TSV尖端，将第一载体从产品晶片的前侧分离出来，以及将薄化的晶片转移到第二载体，其背面粘附到第二晶片载体上。将半导体部件添加到产品晶片的前侧，随后在所加入的半导体部件上形成密封腔，并从产品晶片的背面分离第二载体。拆卸第二个承运人后，晶圆级处理继续。

8. 发明授权

US07396755B2 Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer 有权
标题翻译：高侧壁覆盖超薄金属种子层的工艺和集成方案
公开(公告)号：US07396755B2
公开(公告)日：2008-07-08
申请号：US11126413
申请日：2005-05-11
申请人： Asad M. Haider
发明人： Asad M. Haider
IPC分类号： H01L21/4763
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76865 , H01L21/76873
摘要： The present invention provides a method of forming a metal seed layer 100. The method includes physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also includes a RF plasma etch of the seed metal 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the seed metal 200.
摘要翻译：本发明提供一种形成金属种子层100的方法。该方法包括种子金属200在位于衬底110的电介质层135中的开口140内的物理气相沉积。该方法还包括在进行种子金属200的物理气相沉积的同时沉积在开口140中的种子金属200的RF等离子体蚀刻。

9. 发明授权

US06919233B2 MIM capacitors and methods for fabricating same 有权
标题翻译： MIM电容器及其制造方法
公开(公告)号：US06919233B2
公开(公告)日：2005-07-19
申请号：US10335333
申请日：2002-12-31
申请人： Satyavolu S. Papa Rao , Asad M. Haider , Kelly Taylor , Ed Burke
发明人： Satyavolu S. Papa Rao , Asad M. Haider , Kelly Taylor , Ed Burke
IPC分类号： H01L21/768 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/08 , H01L21/62
CPC分类号： H01L28/40 , H01L27/0805 , Y10T29/417
摘要： Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.
摘要翻译：描述了用于制造其的半导体器件及其制造方法，其中使用单个高k或铁电介质层来形成去耦电容器和模拟电容器段。模拟电容器通过将模拟电容器段彼此串联耦合而形成，其中电容器段可以以相反的极性关系连接，从而为模拟电容器提供对称的性能特性。

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