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1. 发明授权

US5291239A System and method for leveling semiconductor wafers 失效
标题翻译：用于调整半导体晶片的系统和方法
公开(公告)号：US5291239A
公开(公告)日：1994-03-01
申请号：US954516
申请日：1992-09-30
申请人： Ricky A. Jackson
发明人： Ricky A. Jackson
IPC分类号： G03F9/00 , G03B27/42
CPC分类号： G03F9/7069 , G03F9/7034
摘要： A leveling system (10 and 50) with adjustable light beams (38, 53, 55, 59 and 61) is provided for photolithography processes used in manufacturing integrated circuits. The beams (38, 53, 55, 59 and 61) used to assist with positioning wafer (12) relative to the projection camera lens (90) of the step and repeat camera (92) are adjusted for the exposure field (22 and 70) and the desired chip size. For large beam systems (10), the beam width is modified to match the exposure field (22) dimensions which correspond to the desired chip dimensions. For multiple beam systems (50), the geometric relationship of the beams (53, 55, 57, 59 and 61) relative to each other and the desired exposure field (70) are adjusted to provide optimum leveling of the wafer (12) with respect to the projection camera lens (90).
摘要翻译：提供了具有可调节光束（38,53,55,59和61）的调平系统（10和50），用于制造集成电路中的光刻工艺。为了曝光场（22和70）调节用于协助相对于台阶和重复照相机（92）的投影相机透镜（90）定位晶片（12）的光束（38,53,55,59和61））和所需的芯片尺寸。对于大光束系统（10），光束宽度被修改以匹配对应于期望的芯片尺寸的曝光场（22）尺寸。对于多光束系统（50），调节光束（53,55,57,59和61）相对于彼此和期望的曝光场（70）的几何关系，以提供晶片（12）与相对于投影摄像机镜头（90）。

2. 发明授权

US07550046B2 Vapor deposition system using benzotriazole (BTA) and isopropyl alcohol for protecting copper interconnects 有权
标题翻译：使用苯并三唑（BTA）和异丙醇的蒸气沉积系统用于保护铜互连
公开(公告)号：US07550046B2
公开(公告)日：2009-06-23
申请号：US11901180
申请日：2007-09-17
申请人： ChangFeng F. Xia , Arunthathi Sivasothy , Ricky A. Jackson , Asad M. Hauder
发明人： ChangFeng F. Xia , Arunthathi Sivasothy , Ricky A. Jackson , Asad M. Hauder
IPC分类号： C23C16/00
CPC分类号： C23C14/12 , H01L21/76838
摘要： A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.
摘要翻译：提供一种保护互连的方法。该方法包括形成具有互连的集成电路结构，并且在互连上沉积蒸发的苯并三唑。

3. 发明授权

US06687973B2 Optimized metal fuse process 有权
标题翻译：优化金属保险丝工艺
公开(公告)号：US06687973B2
公开(公告)日：2004-02-10
申请号：US09997980
申请日：2001-11-30
申请人： Melissa M. Hewson , Ricky A. Jackson , Abha Singh , Toan Tran , Howard L. Tigelaar
发明人： Melissa M. Hewson , Ricky A. Jackson , Abha Singh , Toan Tran , Howard L. Tigelaar
IPC分类号： H01S400
CPC分类号： H01L23/5258 , H01L2924/0002 , Y10T29/49002 , Y10T29/49107 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
摘要： A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper corners of the fuse (104), the oxide (108) cracks over the fuse (104) during a laser pulse (114). A wet etch is then used to dissolve the exposed fuses (104).
摘要翻译：金属熔断器工艺，其在顶部互连（102）上方使用较薄（例如，6000）的氧化物（108）。在探针焊盘（106）上去除氧化物（108）用于测试，但不在保险丝（104）上移除。因为氧化物（108）在熔丝（104）的上角处较薄，所以氧化物（108）在激光脉冲（114）期间在熔丝（104）上裂开。然后使用湿蚀刻来溶解暴露的熔丝（104）。

4. 发明授权

US5085729A Uniformity using stagnant silylation 失效
标题翻译：均匀性使用停滞的甲硅烷基化
公开(公告)号：US5085729A
公开(公告)日：1992-02-04
申请号：US579120
申请日：1990-09-07
申请人： Cesar M. Garza , Ricky A. Jackson , Ryan E. Priebe
发明人： Cesar M. Garza , Ricky A. Jackson , Ryan E. Priebe
IPC分类号： G03F7/26 , H01L21/3105
CPC分类号： H01L21/31058 , G03F7/265 , Y10S438/948
摘要： A system and method whereby the uniformity of the silylating agent throughout the reaction chamber and primarily at the surface of the wafer is significantly improved to provide a significant improvement in the line width uniformity. In accordance with a first embodiment of the invention, this is accomplished by stagnant silylation wherein the silylating agent is introduced into the reaction chamber and the reaction chamber is then sealed during the entire time required to carry out the silylation. The advantage of this approach is optimum uniformity since once equilibrium has been reached, there is no net change of flow or pressure of the silylating agent across the wafer. Another advantage is reduction in the total consumption of the silylating and carrier gases. In accordance with a second embodiment of the invention, the silylating agent flows laminarly across the surface of the wafer to provide uniformity of the silylating agent at the wafer surface. This is accomplished by introducing the silylating agent and carrier gas along one side of the wafer and uniformly flowing the gases across the entire wafer due to a pressure differential across the wafer from the location(s) of gas entry into the reaction chamber to the location(s) of gas exit from the reaction chamber, for example.
摘要翻译：一种系统和方法，其中遍及反应室和主要在晶片表面的甲硅烷化剂的均匀性得到显着改善，以提供线宽均匀性的显着改进。根据本发明的第一个实施方案，这是通过停滞的甲硅烷基化来完成的，其中将甲硅烷基化剂引入反应室，然后在进行甲硅烷基化所需的整个时间内密封反应室。这种方法的优点是最佳均匀性，因为一旦达到平衡，晶片上的甲硅烷基化剂的流动或压力没有净变化。另一个优点是减少了甲硅烷基化和载气的总消耗。根据本发明的第二个实施方案，甲硅烷基化剂层流地流过晶片的表面，以提供硅烷化剂在晶片表面的均匀性。这是通过沿着晶片的一侧引入甲硅烷基化剂和载体气体并且由于从进入反应室的气体的位置跨过晶片的压差而将气体均匀地流过整个晶片来实现的（例如）从反应室排出的气体。

5. 发明授权

US07144802B2 Vapor deposition of benzotriazole (BTA) for protecting copper interconnects 有权
公开(公告)号：US07144802B2
公开(公告)日：2006-12-05
申请号：US10405590
申请日：2003-04-01
申请人： ChangFeng F. Xia , Arunthathi Sivasothy , Ricky A. Jackson , Asad M. Haider
发明人： ChangFeng F. Xia , Arunthathi Sivasothy , Ricky A. Jackson , Asad M. Haider
IPC分类号： H01L21/4763
CPC分类号： C23C14/12 , H01L21/76838
摘要： A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.

6. 发明授权

US5835196A System and method for alignment of integrated circuits multiple layers 失效
标题翻译：用于集成电路多层对准的系统和方法
公开(公告)号：US5835196A
公开(公告)日：1998-11-10
申请号：US368584
申请日：1995-01-05
申请人： Ricky A. Jackson
发明人： Ricky A. Jackson
IPC分类号： G03F7/20 , G03F9/00 , H01L21/68 , G01B11/00 , G03B27/00
CPC分类号： G03F7/70691 , G03F9/70 , H01L21/681 , Y10S438/975 , Y10T29/41
摘要： An alignment system (30) is provided for use during the lithography process of producing multiple layer (24-26) integrated circuits. The location of each previous layer (24-26) in the integrated circuit is measured and evaluated with respect to each other and the wafer (14). The next layer is placed on the wafer (14) in a manner which optimizes its alignment relationship to each of the previous layers (24-26). Weighting factors are used to optimize alignment in multiple layer (24-26) integrated circuits.
摘要翻译：提供了在制造多层（24-26）集成电路的光刻工艺期间使用的对准系统（30）。集成电路中的每个先前层（24-26）的位置相对于彼此和晶片（14）被测量和评估。下一层以优化其与每个先前层（24-26）的对准关系的方式放置在晶片（14）上。加权因子用于优化多层（24-26）集成电路中的对齐。

7. 发明授权

US5403754A Lithography method for direct alignment of integrated circuits multiple layers 失效
标题翻译：用于集成电路多层直接对准的平版印刷方法
公开(公告)号：US5403754A
公开(公告)日：1995-04-04
申请号：US238194
申请日：1994-05-04
申请人： Ricky A. Jackson
发明人： Ricky A. Jackson
IPC分类号： G03F7/20 , G03F9/00 , H01L21/68 , H01L21/31 , H01L21/312
CPC分类号： G03F7/70691 , G03F9/70 , H01L21/681 , Y10S438/975 , Y10T29/41
摘要： An alignment process (30) for use during the lithography process of producing multiple layer (24-26) integrated circuits. The location of each previous layer (24-26) in the integrated circuit is measured and evaluated with respect to each other and the wafer (14). The next layer is placed on the wafer (14) in a manner which optimizes its alignment relationship to each of the previous layers (24-26). Weighting factors are used to optimize alignment in multiple layer (24-26) integrated circuits.
摘要翻译：在制造多层（24-26）集成电路的光刻工艺期间使用的对准过程（30）。集成电路中的每个先前层（24-26）的位置相对于彼此和晶片（14）被测量和评估。下一层以优化其与每个先前层（24-26）的对准关系的方式放置在晶片（14）上。加权因子用于优化多层（24-26）集成电路中的对齐。

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