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1. 发明申请

US20110114597A1 BARRIER INTEGRATION SCHEME FOR HIGH-RELIABILITY VIAS 审中-公开
标题翻译：用于高可靠性VIAS的障碍整合方案
公开(公告)号：US20110114597A1
公开(公告)日：2011-05-19
申请号：US12834598
申请日：2010-07-12
申请人： Alfred J. Griffin, JR. , Edmund Burke , Asad M. Haider , Kelly J. Taylor , Tae S. Kim
发明人： Alfred J. Griffin, JR. , Edmund Burke , Asad M. Haider , Kelly J. Taylor , Tae S. Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/2855 , H01L21/32131 , H01L21/76805 , H01L21/76829 , H01L21/76844 , H01L21/76846 , H01L21/76847 , H01L21/76867 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.
摘要翻译：公开了一种制造集成电路的方法，包括图案化介电层以形成具有侧壁和底部的孔。孔可以暴露导电材料的下层材料。该方法还包括将侧壁和暴露的下层材料暴露于等离子体蚀刻，在等离子体蚀刻清洁之后，在孔的底部和侧壁上沉积阻挡层，在下面的材料中通过蚀刻通过在孔的底部的阻挡层进入下面的导电金属，将阻挡材料的薄层快速沉积到孔中，最后在覆盖包括锥体的孔的侧壁和底部的孔中沉积金属种子层底端。最后通过在孔中沉积金属层来填充孔。

2. 发明授权

US07332425B2 Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects 有权
标题翻译：用于微电子器件互连中阻挡层形成的同时沉积和蚀刻工艺
公开(公告)号：US07332425B2
公开(公告)日：2008-02-19
申请号：US11126460
申请日：2005-05-11
申请人： Asad M. Haider , Alfred J. Griffin, Jr. , Kelly J. Taylor
发明人： Asad M. Haider , Alfred J. Griffin, Jr. , Kelly J. Taylor
IPC分类号： H01L21/4763
CPC分类号： H01L21/76865 , Y10S438/905
摘要： The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 110. RF plasma etching of the barrier material 200 that is deposited in the opening 140 occurs simultaneously with conducting the physical vapor deposition of the barrier material 200.
摘要翻译：本发明提供一种形成互连阻挡层100的方法。在该方法中，阻挡材料200的物理气相沉积在位于衬底110的电介质层135中的开口140内进行。沉积在开口140中的阻挡材料200的RF等离子体蚀刻与导电阻挡材料200的物理气相沉积同时发生。

3. 发明授权

US07153706B2 Ferroelectric capacitor having a substantially planar dielectric layer and a method of manufacture therefor 有权
标题翻译：具有基本上平面的电介质层的铁电电容器及其制造方法
公开(公告)号：US07153706B2
公开(公告)日：2006-12-26
申请号：US10829053
申请日：2004-04-21
申请人： Sanjeev Aggarwal , Kelly J. Taylor , Lindsey Hall , Satyavolu Srinivas Papa Rao
发明人： Sanjeev Aggarwal , Kelly J. Taylor , Lindsey Hall , Satyavolu Srinivas Papa Rao
IPC分类号： H01L21/00
CPC分类号： H01L27/11585 , H01L21/31053 , H01L27/11502 , H01L27/1159 , H01L28/55
摘要： The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).
摘要翻译：本发明提供一种铁电电容器及其制造方法，以及制造铁电随机存取存储器（FeRAM）器件的方法。除了其他元件之外，铁电电容器（100）包括位于第一电极层（160）上方的基本平坦的铁电介质层（165），其中基本上平坦的铁电介质层（165）的平均表面粗糙度小于约 4nm。铁电电容器（100）还包括位于基本上平坦的铁电介质层（165）上方的第二电极层（170）。

4. 发明授权

US5882981A Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material 失效
标题翻译：采用流化氧化物作为补充材料的绝缘体技术的硅的Mesa隔离再填充工艺
公开(公告)号：US5882981A
公开(公告)日：1999-03-16
申请号：US902010
申请日：1997-07-29
申请人： Rajan Rajgopal , Kelly J. Taylor , Thomas R. Seha , Keith A. Joyner
发明人： Rajan Rajgopal , Kelly J. Taylor , Thomas R. Seha , Keith A. Joyner
IPC分类号： H01L21/314 , H01L21/316 , H01L21/762 , H01L21/225 , H01L21/265
CPC分类号： H01L21/7624 , H01L21/316 , Y10S148/044
摘要： After formation of a sandwich over a substrate of a layer of silicon dioxide (3) followed by a layer of silicon (1) having a pad oxide (7) thereon and a patterned silicon nitride layer (9) over the pad oxide, the unmasked portion of the pad oxide and silicon are removed to provide mesas of silicon with silicon nitride thereover and possibly removal of some of the buried oxide layer. A flowable insulator (15), preferably silsesquioxane (H.sub.x SiO.sub.1.5, where x.ltoreq.1, depending upon the level of polymerization) in a contaminant-free, high purity solvent which is later removed during an annealing step, is placed over the exposed surface such that it fills the voids between the mesas of silicon with silicon nitride thereon and extends over the nitride. The flowable insulator, due to its flowability, provides a generally planar surface. The flowable insulator is etched back and a cap oxide (17) is optionally deposited over the etched back insulator layer. The cap oxide layer (if used), some insulator and nitride are then etched away, leaving the pad oxide over the silicon. The processing is then completed by removing the pad oxide, growing a gate oxide and then forming the gate and source drain electrodes and/or other processing techniques that may be required to provide the final device.
摘要翻译：在二氧化硅（3）的衬底上形成三明治，然后在其上具有衬垫氧化物（7）的硅层（1）和衬垫氧化物上的图案化氮化硅层（9）之后，未掩模去除衬垫氧化物和硅的一部分以提供硅的台面与其上的氮化硅，并且可能去除一些掩埋氧化物层。在退火步骤中随后除去的无污染物，高纯度溶剂中的可流动绝缘体（15），优选倍半硅氧烷（H x SiO 1.5，其中x 1取决于聚合水平）放置在暴露的表面，使得其填充硅之间的间隙与其上的氮化硅之间的空隙并且在氮化物上延伸。可流动的绝缘体由于其流动性而提供了大致平坦的表面。可流动的绝缘体被回蚀刻，并且可选地，在氧化蚀刻的背面绝缘体层上沉积氧化碳（17）。盖氧化物层（如果使用），然后蚀刻掉一些绝缘体和氮化物，使衬垫氧化物留在硅上。然后通过去除衬垫氧化物，生长栅极氧化物，然后形成栅极和源极漏极和/或可能需要提供最终器件的其它处理技术来完成处理。

5. 发明授权

US10011142B1 Large format erasable writable surfaces 有权
公开(公告)号：US10011142B1
公开(公告)日：2018-07-03
申请号：US15721398
申请日：2017-09-29
申请人： Kelly J. Taylor
发明人： Kelly J. Taylor
IPC分类号： B43L1/00 , B32B3/30 , B32B7/12 , B32B7/06 , B32B27/30 , B32B27/36 , B32B27/08
CPC分类号： B43L1/002 , B32B3/30 , B32B7/06 , B32B7/12 , B32B27/08 , B32B27/304 , B32B27/36 , B32B2307/412 , B32B2307/536 , B43L1/00
摘要： An erasable writable material for large format applications is disclosed, and includes a cast polyvinylchloride film with a mount surface opposite an etched receiver surface. Also incorporated is a transparent polyester film that has a marking side with a hardness exceeding approximately shore D 79 and an opposite seal side, hermetically laminated to the receiver surface. The marking side includes a clear superstrate that has a hardness exceeding approximately shore D 90, which is applied to the marking side of the polyester film to lower surface energy below about 24 millinewtons per meter. The receiver surface is treated to have a surface energy exceeding about 45 millinewtons per meter, to enable improved adherence of printed and preformed graphic elements, which are encapsulated when laminated between the PET film and receiver surface. The superstrate includes a perfluoropolyether, a polyurethane, an acrylated polyurethane, and/or an acrylate resin to harden the material.

6. 发明授权

US07001821B2 Method of forming and using a hardmask for forming ferroelectric capacitors in a semiconductor device 有权
标题翻译：在半导体器件中形成和使用用于形成铁电电容器的硬掩模的方法
公开(公告)号：US07001821B2
公开(公告)日：2006-02-21
申请号：US10705039
申请日：2003-11-10
申请人： Sanjeev Aggarwal , Kelly J. Taylor , Theodore S. Moise
发明人： Sanjeev Aggarwal , Kelly J. Taylor , Theodore S. Moise
IPC分类号： H01L21/20
CPC分类号： H01L27/11502 , H01L21/28568 , H01L21/31122 , H01L21/32136 , H01L21/32139 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.
摘要翻译：硬掩模和制造方法用于在半导体器件中制造铁电电容器，其中在上部电容器电极材料上方形成包括氧化铝或氧化钽锶的硬掩模，并蚀刻电容器电极和铁电层以限定铁电电容器叠层。

7. 发明授权

US06465350B1 Aluminum nitride thin film formation on integrated circuits 有权
标题翻译：集成电路上的氮化铝薄膜形成
公开(公告)号：US06465350B1
公开(公告)日：2002-10-15
申请号：US09689077
申请日：2000-10-12
申请人： Kelly J. Taylor , Wei-Yan Shih
发明人： Kelly J. Taylor , Wei-Yan Shih
IPC分类号： H01L2144
CPC分类号： H01L21/76888 , H01L21/318 , H01L21/76834
摘要： A method for forming a thin aluminum-nitride film (112). Solid hydrazine cyanurate is heated to produce in-situ hydrazine (N2H4). The in-situ hydrazine reacts with a previously deposited ailminum layer (108) to form aluminum-nitride (112).
摘要翻译：一种形成薄的氮化铝膜（112）的方法。将固体肼氰脲酸酯加热以产生原位肼（N 2 H 4）。原位肼与先前沉积的氧化铝层（108）反应形成氮化铝（112）。

8. 发明授权

US06351039B1 Integrated circuit dielectric and method 失效
标题翻译：集成电路电介质和方法
公开(公告)号：US06351039B1
公开(公告)日：2002-02-26
申请号：US09087457
申请日：1998-05-28
申请人： Changming Jin , Kelly J. Taylor , Wei William Lee
发明人： Changming Jin , Kelly J. Taylor , Wei William Lee
IPC分类号： H01L2348
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/0234 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/3105 , H01L21/31695 , H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L21/76837 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).
摘要翻译：用于多孔二氧化硅的表面处理以增强上覆层的粘附力。处理包括侵入干凝胶（510）的开放表面孔（514）的表面取代，孔塌陷和间隙填充层（520）。

9. 发明授权

US5888905A Integrated circuit insulator and method 失效
标题翻译：集成电路绝缘子及方法
公开(公告)号：US5888905A
公开(公告)日：1999-03-30
申请号：US965080
申请日：1997-11-06
申请人： Kelly J. Taylor , Mona Eissa
发明人： Kelly J. Taylor , Mona Eissa
IPC分类号： H01L21/312 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/302
CPC分类号： H01L23/5329 , H01L21/312 , H01L21/76801 , H01L21/76835 , H01L23/5222 , H01L2924/0002
摘要： A intermetal level dielectrics with fluorinated (co)polymers of parylene (142) between metal lines (112-120), and vapor deposition method for the (co)polymerization followed by fluorination of the (co)polymers.
摘要翻译：在金属线（112-120）之间具有聚对二甲苯（142）的氟化（共）聚合物的金属间电介质和用于（共）聚合的气相沉积方法，然后氟化（共）聚合物。

10. 发明授权

US11772410B1 Erasable writable materials 有权
公开(公告)号：US11772410B1
公开(公告)日：2023-10-03
申请号：US17333636
申请日：2021-05-28
申请人： Kelly J. Taylor
发明人： Kelly J. Taylor
IPC分类号： B43L1/00 , B32B3/30 , B32B7/06 , B32B7/12 , B32B27/30 , B32B27/36 , B32B27/08
CPC分类号： B43L1/002 , B32B3/30 , B32B7/06 , B32B7/12 , B32B27/08 , B32B27/304 , B32B27/36 , B32B2307/412 , B32B2307/536
摘要： A magnetic erasable writable material for large format applications is disclosed, and includes a cast polyvinylchloride film with a mount surface opposite an etched receiver surface. Also incorporated is a transparent polyester film that has a marking side with a first predetermined hardness and an opposite seal side, laminated to the receiver surface. The marking side includes a clear superstrate that has a second predetermined hardness and applied to the marking side of the polyester film to lower its surface energy. The receiver surface is treated to have a surface energy adjusted to enable improved adherence of printed and preformed graphic elements, which are encapsulated when laminated between the PET film and receiver surface. The superstrate includes a perfluoropolyether, a polyurethane, an acrylated polyurethane, and/or an acrylate resin to harden the material.

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