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1. 发明授权

US09075913B2 Validation of applications for graphics processing unit 有权
标题翻译：验证图形处理单元的应用程序
公开(公告)号：US09075913B2
公开(公告)日：2015-07-07
申请号：US13406272
申请日：2012-02-27
申请人： Alexei V. Bourd , Jay Chunsup Yun
发明人： Alexei V. Bourd , Jay Chunsup Yun
IPC分类号： G06F9/45 , G06F9/44 , G06F21/00 , G06F11/36 , G06F11/07 , G06F21/56
CPC分类号： G06F11/3604 , G06F8/30 , G06F11/0736 , G06F11/0751 , G06F11/0793 , G06F11/3612 , G06F11/3652 , G06F11/3664 , G06F21/566 , G06F2221/033
摘要： The techniques described in this disclosure are directed to validating an application that is to be executed on a graphics processing unit (GPU). For example, a validation server device may receive code of the application. The validation server device may provide some level of assurance that the application satisfies one or more performance criteria. In this manner, the probability of a problematic application executing on the device that includes the GPU may be reduced.
摘要翻译：本公开中描述的技术旨在验证将在图形处理单元（GPU）上执行的应用。例如，验证服务器设备可以接收应用的代码。验证服务器设备可以提供应用满足一个或多个性能标准的一定程度的保证。以这种方式，可以减少在包括GPU的设备上执行有问题的应用的概率。

2. 发明申请

US20130227521A1 VALIDATION OF APPLICATIONS FOR GRAPHICS PROCESSING UNIT 有权
公开(公告)号：US20130227521A1
公开(公告)日：2013-08-29
申请号：US13406272
申请日：2012-02-27
申请人： Alexei V. Bourd , Jay Chunsup Yun
发明人： Alexei V. Bourd , Jay Chunsup Yun
IPC分类号： G06F9/44 , G06F9/45 , G06F21/00
CPC分类号： G06F11/3604 , G06F8/30 , G06F11/0736 , G06F11/0751 , G06F11/0793 , G06F11/3612 , G06F11/3652 , G06F11/3664 , G06F21/566 , G06F2221/033
摘要： The techniques described in this disclosure are directed to validating an application that is to be executed on a graphics processing unit (GPU). For example, a validation server device may receive code of the application. The validation server device may provide some level of assurance that the application satisfies one or more performance criteria. In this manner, the probability of a problematic application executing on the device that includes the GPU may be reduced.

3. 发明申请

US20100141659A1 DISCARDING OF VERTEX POINTS DURING TWO-DIMENSIONAL GRAPHICS RENDERING USING THREE-DIMENSIONAL GRAPHICS HARDWARE 有权
标题翻译：在使用三维图形硬件的二维图形渲染期间对VERTEX点进行分类
公开(公告)号：US20100141659A1
公开(公告)日：2010-06-10
申请号：US12331273
申请日：2008-12-09
申请人： ALEXEI V. BOURD , Guofang Jiao , Jay Chunsup Yun
发明人： ALEXEI V. BOURD , Guofang Jiao , Jay Chunsup Yun
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： This disclosure describes techniques for removing vertex points during two-dimensional (2D) graphics rendering using three-dimensional (3D) graphics hardware. In accordance with the described techniques one or more vertex points may be removed during 2D graphics rendering using 3D graphics hardware. For example, the techniques may remove redundant vertex points in the display coordinate space by discarding vertex points that have the substantially same positional coordinates in the display coordinate space as a previous vertex point. Alternatively or additionally, the techniques may remove excess vertex points that lie in a straight line. Removing the redundant vertex points or vertex points that lie in a straight line allow for more efficient utilization of the hardware resources of the GPU and increase the speed at which the GPU renders the image for display.
摘要翻译：本公开描述了使用三维（3D）图形硬件在二维（2D）图形渲染期间去除顶点的技术。根据描述的技术，可以使用3D图形硬件在2D图形渲染期间移除一个或多个顶点。例如，这些技术可以通过丢弃在显示坐标空间中具有与先前顶点相同的位置坐标的顶点来去除显示坐标空间中的冗余顶点。或者或另外，这些技术可以去除位于直线上的多余顶点。去除位于直线上的冗余顶点或顶点可以更有效地利用GPU的硬件资源，并提高GPU渲染图像以进行显示的速度。

4. 发明授权

US07921274B2 Computer memory addressing mode employing memory segmenting and masking 有权
标题翻译：采用存储器分割和掩蔽的计算机存储器寻址模式
公开(公告)号：US07921274B2
公开(公告)日：2011-04-05
申请号：US11737206
申请日：2007-04-19
申请人： Bo Zhang , Guofang Jiao , Yun Du , Jay Chunsup Yun
发明人： Bo Zhang , Guofang Jiao , Yun Du , Jay Chunsup Yun
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/345 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/30138 , G06F9/3016 , G06F9/342 , G06F9/3877
摘要： A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed.
摘要翻译：计算机寻址模式和存储器访问方法依赖于存储器段标识符和用于指示存储器位置的存储器段掩码。在该寻址模式中，处理器接收包括存储器段标识符和存储器段掩码的指令。处理器采用两级地址解码方案来访问各个存储单元。在该解码方案下，处理器解码存储器段标识符以选择特定存储器段。每个存储器段包括预定义数量的存储器位置。处理器基于在存储器段掩码中设置的掩码位来选择存储器段内的存储器位置。所公开的寻址模式是有利的，因为它允许有效地访问非连续存储器位置。

5. 发明申请

US20080263315A1 COMPUTER MEMORY ADDRESSING MODE EMPLOYING MEMORY SEGMENTING AND MASKING 有权
标题翻译：使用内存分割和掩码的计算机存储器寻址模式
公开(公告)号：US20080263315A1
公开(公告)日：2008-10-23
申请号：US11737206
申请日：2007-04-19
申请人： Bo Zhang , Guofang Jiao , Yun Du , Jay Chunsup Yun
发明人： Bo Zhang , Guofang Jiao , Yun Du , Jay Chunsup Yun
IPC分类号： G06F9/26
CPC分类号： G06F9/345 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/30138 , G06F9/3016 , G06F9/342 , G06F9/3877
摘要： A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed.
摘要翻译：计算机寻址模式和存储器访问方法依赖于存储器段标识符和用于指示存储器位置的存储器段掩码。在该寻址模式中，处理器接收包括存储器段标识符和存储器段掩码的指令。处理器采用两级地址解码方案来访问各个存储单元。在该解码方案下，处理器解码存储器段标识符以选择特定存储器段。每个存储器段包括预定义数量的存储器位置。处理器基于在存储器段掩码中设置的掩码位来选择存储器段内的存储器位置。所公开的寻址模式是有利的，因为它允许有效地访问非连续存储器位置。

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