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1. 发明申请

US20060101369A1 Automated processor generation system for designing a configurable processor and method for the same 失效
标题翻译：用于设计可配置处理器的自动处理器生成系统及其方法
公开(公告)号：US20060101369A1
公开(公告)日：2006-05-11
申请号：US11281217
申请日：2005-11-16
申请人： Albert Wang , Richard Ruddell , David Goodwin , Earl Killian , Nupur Bhattacharyya , Marines Medina , Walter Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Songer , Akilesh Parameswar , Dror Maydan , Ricardo Gonzalez
发明人： Albert Wang , Richard Ruddell , David Goodwin , Earl Killian , Nupur Bhattacharyya , Marines Medina , Walter Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Songer , Akilesh Parameswar , Dror Maydan , Ricardo Gonzalez
IPC分类号： G06F17/50
CPC分类号： G06F9/30167 , G06F9/30145 , G06F17/5045
摘要： A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
摘要翻译：用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。另外，系统从语言规范生成格式化指令集文档。

2. 发明申请

US20060259878A1 Automated processor generation system for designing a configurable processor and method for the same 有权
公开(公告)号：US20060259878A1
公开(公告)日：2006-11-16
申请号：US11391773
申请日：2006-03-27
申请人： Earl Killian , Ricardo Gonzalez , Ashish Dixit , Monica Lam , Walter Lichtenstein , Christopher Rowen , John Ruttenberg , Robert Wilson , Albert Wang , Dror Maydan
发明人： Earl Killian , Ricardo Gonzalez , Ashish Dixit , Monica Lam , Walter Lichtenstein , Christopher Rowen , John Ruttenberg , Robert Wilson , Albert Wang , Dror Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/20 , G06F8/41 , G06F8/53 , G06F2217/04 , G06F2217/68
摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

3. 发明申请

US20050278713A1 Automatic instruction set architecture generation 有权
公开(公告)号：US20050278713A1
公开(公告)日：2005-12-15
申请号：US11208239
申请日：2005-08-18
申请人： David Goodwin , Dror Maydan , Ding-Kai Chen , Darin Petkov , Steven Tjiang , Peng Tu , Christopher Rowen
发明人： David Goodwin , Dror Maydan , Ding-Kai Chen , Darin Petkov , Steven Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/30 , G06F9/45 , G06F17/50
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

4. 发明授权

US07971197B2 Automatic instruction set architecture generation 有权
标题翻译：自动指令集架构生成
公开(公告)号：US07971197B2
公开(公告)日：2011-06-28
申请号：US11208239
申请日：2005-08-18
申请人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
发明人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/45 , G06F15/00 , G06F15/76
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
摘要翻译：数字计算机系统自动创建可能利用VLIW指令，向量操作，融合操作和专门操作的指令集体系结构（ISA），目的是提高一组应用程序的性能，同时保持硬件成本低于设计者指定的限制，或者为了降低硬件成本，为达到所需的性能水平。

5. 发明授权

US06941548B2 Automatic instruction set architecture generation 有权
标题翻译：自动指令集架构生成
公开(公告)号：US06941548B2
公开(公告)日：2005-09-06
申请号：US09981291
申请日：2001-10-16
申请人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
发明人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/30 , G06F9/45 , G06F17/50
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
摘要翻译：数字计算机系统自动创建可能利用VLIW指令，向量操作，融合操作和专门操作的指令集体系结构（ISA），目的是提高一组应用程序的性能，同时保持硬件成本低于设计者指定的限制，或者为了降低硬件成本，为达到所需的性能水平。

6. 发明授权

US06226790B1 Method for selecting optimal parameters for compiling source code 失效
标题翻译：选择用于编译源代码的最优参数的方法
公开(公告)号：US06226790B1
公开(公告)日：2001-05-01
申请号：US08808224
申请日：1997-02-28
申请人： Michael Wolf , Dror Maydan
发明人： Michael Wolf , Dror Maydan
IPC分类号： G06F9445
CPC分类号： G06F8/4441
摘要： In a computer system, a method for determining an optimal loop interchange, set of register tiling amount, and cache tiling size for compiling source code into object code. The method first constructs a model of the specific computer system upon which the object code is to be run. Next, the search space comprising all of the different possibilities of the loop interchanges, register tiling amounts, and cache tiling sizes is run through the model to determine estimated times of execution. The particular loop interchange, set of register tiling amounts, and cache tiling sizes corresponding to the best estimated time of execution is then selected as being the most optimal. The source code is then compiled according to this optimal loop interchange, register tiling amount, and cache tiling size.
摘要翻译：在计算机系统中，确定用于将源代码编译成对象代码的最佳循环交换，寄存器平铺量的集合和高速缓存平铺大小的方法。该方法首先构建要在其上运行目标代码的特定计算机系统的模型。接下来，通过该模型运行包括循环交换，寄存器堆叠量和高速缓存分块大小的所有不同可能性的搜索空间，以确定估计的执行时间。然后选择特定的循环交换，寄存器堆叠量的集合和对应于最佳估计执行时间的高速缓存平铺大小作为最优。然后根据这个最佳循环交换，寄存器平铺量和缓存平铺大小来编译源代码。

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