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1. 发明申请

US20060101369A1 Automated processor generation system for designing a configurable processor and method for the same 失效
标题翻译：用于设计可配置处理器的自动处理器生成系统及其方法
公开(公告)号：US20060101369A1
公开(公告)日：2006-05-11
申请号：US11281217
申请日：2005-11-16
申请人： Albert Wang , Richard Ruddell , David Goodwin , Earl Killian , Nupur Bhattacharyya , Marines Medina , Walter Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Songer , Akilesh Parameswar , Dror Maydan , Ricardo Gonzalez
发明人： Albert Wang , Richard Ruddell , David Goodwin , Earl Killian , Nupur Bhattacharyya , Marines Medina , Walter Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Songer , Akilesh Parameswar , Dror Maydan , Ricardo Gonzalez
IPC分类号： G06F17/50
CPC分类号： G06F9/30167 , G06F9/30145 , G06F17/5045
摘要： A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
摘要翻译：用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。另外，系统从语言规范生成格式化指令集文档。

2. 发明授权

US07249351B1 System and method for preparing software for execution in a dynamically configurable hardware environment 有权
标题翻译：用于在可动态配置的硬件环境中准备执行软件的系统和方法
公开(公告)号：US07249351B1
公开(公告)日：2007-07-24
申请号：US09651425
申请日：2000-08-30
申请人： Christopher Songer , Ian S. Eslick , Robert S. French
发明人： Christopher Songer , Ian S. Eslick , Robert S. French
IPC分类号： G06F9/45
CPC分类号： G06F8/451
摘要： A system and method for creating run time executables in a configurable processing element array is disclosed. This system and method includes the step of partitioning a processing element array into a number of defined sets of hardware accelerators, which in one embodiment are processing elements called “bins”. The system and method then involves decomposing a program description in object code form into a plurality of “kernel sections”, where the kernel sections are defined as those sections of object code which are candidates for hardware acceleration. Next, mapping the identified kernel sections into a number of hardware dependent designs is performed. Finally, a matrix of the bins and the designs is formed for use by the run time system.
摘要翻译：公开了一种用于在可配置处理元件阵列中创建运行时可执行体的系统和方法。该系统和方法包括将处理元件阵列分割成多个定义的硬件加速器组的步骤，在一个实施例中，这些硬件加速器在处理元件中被称为“仓”。然后，系统和方法包括将目标代码形式的程序描述分解成多个“核心部分”，其中内核部分被定义为作为硬件加速候选的目标代码的那些部分。接下来，执行将所识别的内核部分映射到多个与硬件有关的设计。最后，形成箱体和设计的矩阵以供运行时间系统使用。

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