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1. 发明授权

US06185713B2 Method and apparatus for improving stuck-at fault detection in large scale integrated circuit testing 失效
标题翻译：用于改进大规模集成电路测试中的故障检测的方法和装置
公开(公告)号：US06185713B2
公开(公告)日：2001-02-06
申请号：US09057507
申请日：1998-04-09
申请人： Alan Nakamoto , Kris Iniewski , Monika Swic , Curtis Lapadat , Larrie Simon Carr
发明人： Alan Nakamoto , Kris Iniewski , Monika Swic , Curtis Lapadat , Larrie Simon Carr
IPC分类号： G01R3128
CPC分类号： G01R31/318371 , G11C29/50
摘要： A bus holder for coupling to an integrated circuit bus driven by a plurality of tri-state devices. The bus holder has a bidirectional port and first and second test ports. Logic circuitry coupled between the respective ports is configured such that application of a logic 0 to the first test port causes the bidirectional port to drive whatever logic value is applied to that port; application of a logic 1 to the first test port and application of a logic 0 to the second test port pulls the bidirectional port down to a logic 0; and, application of a logic 1 to both the first and second test ports pulls the bidirectional port up to a logic 1.
摘要翻译：一种用于耦合到由多个三态装置驱动的集成电路总线的总线保持器。总线支架具有双向端口和第一和第二测试端口。耦合在相应端口之间的逻辑电路被配置为使得逻辑0到第一测试端口的应用导致双向端口驱动应用于该端口的任何逻辑值; 将逻辑1应用于第一测试端口并将逻辑0应用于第二测试端口将双向端口降低到逻辑0; 并且将逻辑1应用于第一和第二测试端口将双向端口拉至逻辑1。

2. 发明授权

US5734541A Low voltage silicon controlled rectifier structure for ESD input pad protection in CMOS IC's 失效
标题翻译： CMOS IC的ESD输入焊盘保护的低压可控硅整流器结构
公开(公告)号：US5734541A
公开(公告)日：1998-03-31
申请号：US650836
申请日：1996-05-20
申请人： Kris Iniewski , Brian D. Gerson , Colin Harris , David LeBlanc
发明人： Kris Iniewski , Brian D. Gerson , Colin Harris , David LeBlanc
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H02H3/22
CPC分类号： H01L27/0262 , H01L27/0266 , H01L2924/0002
摘要： An electrostatic discharge (ESD) protection structure for protection of a circuit to which an operation voltage is to be applied, comprising a silicon controlled rectifier (SCR) connected between ground and a pad of the circuit to be protected, the SCR including a resistor apparatus connected to the pad for controlling the breakdown voltage of the SCR, and apparatus for controlling the resistor apparatus to a high resistance value in the absence of the application of the operation voltage whereby the SCR is controlled to break down at a low ESD voltage which is lower than a circuit damaging voltage, and to be of low resistance value upon the application of the operation voltage whereby the SCR is controlled to break down at an ESD voltage which is higher than the low ESD voltage.
摘要翻译：一种用于保护要施加操作电压的电路的静电放电（ESD）保护结构，包括连接在接地和待保护电路的焊盘之间的可控硅整流器（SCR），所述SCR包括电阻器装置连接到焊盘，用于控制SCR的击穿电压;以及用于在没有施加操作电压的情况下将电阻器设备控制为高电阻值的装置，由此SCR被控制为在低ESD电压下分解，低于电路损坏电压，并且在施加操作电压时具有低电阻值，由此SCR被控制为在高于低ESD电压的ESD电压下分解。

3. 发明授权

US6128171A Gate-coupled structure for enhanced ESD input/output pad protection in CMOS ICs 有权
标题翻译：栅极耦合结构，用于在CMOS IC中增强ESD输入/输出焊盘保护
公开(公告)号：US6128171A
公开(公告)日：2000-10-03
申请号：US236100
申请日：1999-01-25
申请人： Kris Iniewski , Marek Syrzycki
发明人： Kris Iniewski , Marek Syrzycki
IPC分类号： H01L23/60 , H02H9/00
CPC分类号： H02H9/046 , H01L24/05 , H01L2224/05554 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14
摘要： An electrostatic discharge protection circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first switch apparatus comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain and substrate of the second NMOS FET connected to Vss, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.
摘要翻译：一种静电放电保护电路，包括静电放电输入节点，第一NMOS FET，其漏极连接到输入节点，其源极和基板连接到Vss;第一开关装置，包括第一PMOS FET和第二NMOS FET，连接到输入节点的第一PMOS FET的源极和衬底，连接到Vss的第二NMOS FET的漏极和衬底，连接到第二NMOS FET的漏极的第一PMOS FET的漏极和栅极的第一PMOS FET和连接到Vdd的第二NMOS FET以及连接到第一NMOS FET的栅极的结。

4. 发明授权

US6075419A High speed wide tuning range multi-phase output ring oscillator 有权
标题翻译：高速宽调谐范围多相输出环形振荡器
公开(公告)号：US6075419A
公开(公告)日：2000-06-13
申请号：US239311
申请日：1999-01-29
申请人： Lizhong Sun , Tadeusz Kwasniewski , Kris Iniewski
发明人： Lizhong Sun , Tadeusz Kwasniewski , Kris Iniewski
IPC分类号： H03B27/00 , H03B5/02
CPC分类号： H03B27/00
摘要： A ring oscillator comprising: a plurality of sub-feedback loops, each comprising a pair of serially connected inverters and a feedback inverter having its input coupled to the output of the pair of inverters and its output connected to the input of the pair of inverters, the pairs of inverters being connected in a ring, and a downstream inverter of each respective pair of inverters forming an upstream inverter of an immediately following pair of inverters.
摘要翻译：一种环形振荡器，包括：多个子反馈回路，每个子反馈回路包括一对串联的反相器和反相反相器，其反相器的输入耦合到该对反相器的输出端，其输出端连接到该对反相器的输入端，成对的逆变器以环形连接，并且每对逆变器的下游逆变器形成紧随其后的一对逆变器的上游逆变器。

5. 发明授权

US6104277A Polysilicon defined diffused resistor 失效
标题翻译：多晶硅限定扩散电阻
公开(公告)号：US6104277A
公开(公告)日：2000-08-15
申请号：US866106
申请日：1997-05-30
申请人： Kris Iniewski , Brian D. Gerson , Colin Harris , David LeBlanc
发明人： Kris Iniewski , Brian D. Gerson , Colin Harris , David LeBlanc
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06 , H01L27/08 , H01L29/8605 , H01C1/012
CPC分类号： H01L27/0629 , H01L27/0802 , H01L29/8605
摘要： A resistor having a diffused impurity region in a semiconductor substrate, an insulated gate surrounding and defining the resistor, and a pair of separated conductive contacts to the diffused region within the boundary of the insulated gate for applying and receiving current passing through the resistor.
摘要翻译：一种在半导体衬底中具有扩散杂质区域的电阻器，围绕并限定电阻器的绝缘栅极，以及在绝缘栅极的边界内的扩散区域的一对分离的导电触点，用于施加和接收通过电阻器的电流。

6. 发明授权

US5760618A Process compensated integrated circuit output driver 失效
标题翻译：过程补偿集成电路输出驱动器
公开(公告)号：US5760618A
公开(公告)日：1998-06-02
申请号：US664119
申请日：1996-06-14
申请人： George Deliyannides , Kris Iniewski
发明人： George Deliyannides , Kris Iniewski
IPC分类号： H03K19/003 , H03K3/00
CPC分类号： H03K19/00384
摘要： An integrated circuit output driver which reduces the effect of power supply and/or integrated circuit fabrication process variations on signal propagation delay. The output driver produces an output signal V.sub.out as an increased drive strength replica of an input signal V.sub.in. A pre-driver receives V.sub.in and produces an intermediate, inverted replica V.sub.int thereof. A driver is electrically connected to the pre-driver's output to receive V.sub.int. V.sub.out appears at the driver's output as an inverted, strengthened replica of V.sub.int. A first feedback circuit electrically connected between the driver's input and output applies a pull-down signal to the driver's input in response to a falling edge of V.sub.in, with the pull-down signal's strength varying in inverse proportion to propagation delay of the falling edge of V.sub.in. A second feedback circuit electrically connected between the driver's input and output applies a pull-up signal to the driver's input in response to a rising edge of V.sub.in, with the pull-up signal's varying in inverse proportion to propagation delay of the rising edge of V.sub.in.
摘要翻译：集成电路输出驱动器，其减少电源和/或集成电路制造工艺变化对信号传播延迟的影响。输出驱动器产生输出信号Vout作为输入信号Vin的增加的驱动强度副本。预驱动器接收Vin并产生中间的，反向的副本Vint。驱动器电连接到前驱动器的输出端以接收Vint。 VOUT出现在驾驶员输出处，作为反转，强化的Vint副本。电连接在驱动器的输入和输出之间的第一反馈电路响应于Vin的下降沿向驱动器的输入施加下拉信号，其中下拉信号的强度与下降沿的传播延迟成反比 Vin。电连接在驱动器的输入和输出之间的第二反馈电路响应于Vin的上升沿而向驱动器的输入端施加上拉信号，上拉信号与Vin的上升沿的传播延迟成反比变化。

7. 发明授权

US5973977A Poly fuses in CMOS integrated circuits 失效
标题翻译： CMOS集成电路中的Poly保险丝
公开(公告)号：US5973977A
公开(公告)日：1999-10-26
申请号：US110206
申请日：1998-07-06
申请人： Graeme B. Boyd , Kris Iniewski
发明人： Graeme B. Boyd , Kris Iniewski
IPC分类号： G11C17/16 , G11C7/00
CPC分类号： G11C17/16
摘要： An integrated circuit fuse with a fuse element having an "open" state and a "closed" state. A fuse status indicator is provided to indicate whether the fuse element is "open" or "closed". A current driver is electrically connected between the fuse element and electrical ground. One input of a dual input multiplexer is electrically connected to the fuse status indicator. The multiplexer's other input receives a fuse status simulation signal. A simulation mode switching signal is applied to the multiplexer's select input. A fuse output signal is consequently provided at the multiplexer's output to simulate operation of the fuse element in either the "open" or the "closed" state. The fuse element can be opened by causing a current having a value exceeding a preselected minimum value to flow through the fuse element for a preselected minimum time. This is preferably accomplished by fabricating the current driver as an NMOS device having a size sufficiently large to conduct the minimum value current for the minimum time required to open the fuse element. Advantageously, a pre-driver is provided to rapidly turn the current driver on, upon receipt of a fuse opening signal.
摘要翻译：一种具有“断开”状态和“闭合”状态的保险丝元件的集成电路保险丝。提供保险丝状态指示器以指示保险丝元件是“开路”还是“闭合”。电流驱动器电连接在熔丝元件和电气接地之间。双输入多路复用器的一个输入电连接到保险丝状态指示器。多路复用器的其他输入接收保险丝状态模拟信号。模拟模式切换信号被施加到多路复用器的选择输入。因此，熔丝输出信号被提供在多路复用器的输出处以模拟“开路”或“闭合”状态下的熔丝元件的操作。可以通过使具有超过预选最小值的值的电流流过保险丝元件达预选的最小时间来打开熔丝元件。这优选通过制造电流驱动器作为具有足够大的尺寸的NMOS器件来实现，以便在打开熔丝元件所需的最短时间内传导最小值电流。有利地，提供预驱动器以在接收到保险丝开启信号时快速地转动电流驱动器。

8. 发明授权

US5910874A Gate-coupled structure for enhanced ESD input/output pad protection in CMOS ICs 失效
标题翻译：栅极耦合结构，用于在CMOS IC中增强ESD输入/输出焊盘保护
公开(公告)号：US5910874A
公开(公告)日：1999-06-08
申请号：US866120
申请日：1997-05-30
申请人： Kris Iniewski , Marek Syrzycki
发明人： Kris Iniewski , Marek Syrzycki
IPC分类号： H01L23/60 , H02H9/00
CPC分类号： H02H9/046 , H01L24/05 , H01L2224/05554 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14
摘要： An electrostatic discharge circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first CMOS inverter comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the source of the second NMOS FET connected to Vss, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.
摘要翻译：一种静电放电电路，包括静电放电输入节点，其漏极连接到输入节点并且其源极和衬底连接到Vss的第一NMOS FET，由第一PMOS FET和具有源极的第二NMOS FET组成的第一CMOS反相器和连接到输入节点的第一PMOS FET的衬底，连接到第二NMOS FET的漏极的第一PMOS FET的漏极和连接到Vss的第二NMOS FET的源极，以及栅极第一PMOS FET和连接到Vdd的第二NMOS FET以及连接到第一NMOS FET的栅极的结。

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