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1. 发明授权

US5760618A Process compensated integrated circuit output driver 失效
标题翻译：过程补偿集成电路输出驱动器
公开(公告)号：US5760618A
公开(公告)日：1998-06-02
申请号：US664119
申请日：1996-06-14
申请人： George Deliyannides , Kris Iniewski
发明人： George Deliyannides , Kris Iniewski
IPC分类号： H03K19/003 , H03K3/00
CPC分类号： H03K19/00384
摘要： An integrated circuit output driver which reduces the effect of power supply and/or integrated circuit fabrication process variations on signal propagation delay. The output driver produces an output signal V.sub.out as an increased drive strength replica of an input signal V.sub.in. A pre-driver receives V.sub.in and produces an intermediate, inverted replica V.sub.int thereof. A driver is electrically connected to the pre-driver's output to receive V.sub.int. V.sub.out appears at the driver's output as an inverted, strengthened replica of V.sub.int. A first feedback circuit electrically connected between the driver's input and output applies a pull-down signal to the driver's input in response to a falling edge of V.sub.in, with the pull-down signal's strength varying in inverse proportion to propagation delay of the falling edge of V.sub.in. A second feedback circuit electrically connected between the driver's input and output applies a pull-up signal to the driver's input in response to a rising edge of V.sub.in, with the pull-up signal's varying in inverse proportion to propagation delay of the rising edge of V.sub.in.
摘要翻译：集成电路输出驱动器，其减少电源和/或集成电路制造工艺变化对信号传播延迟的影响。输出驱动器产生输出信号Vout作为输入信号Vin的增加的驱动强度副本。预驱动器接收Vin并产生中间的，反向的副本Vint。驱动器电连接到前驱动器的输出端以接收Vint。 VOUT出现在驾驶员输出处，作为反转，强化的Vint副本。电连接在驱动器的输入和输出之间的第一反馈电路响应于Vin的下降沿向驱动器的输入施加下拉信号，其中下拉信号的强度与下降沿的传播延迟成反比 Vin。电连接在驱动器的输入和输出之间的第二反馈电路响应于Vin的上升沿而向驱动器的输入端施加上拉信号，上拉信号与Vin的上升沿的传播延迟成反比变化。

2. 发明授权

US5959490A High speed low voltage swing receiver for mixed supply voltage interfaces 失效
标题翻译：用于混合电源电压接口的高速低压摆动接收器
公开(公告)号：US5959490A
公开(公告)日：1999-09-28
申请号：US987446
申请日：1997-12-10
申请人： Anthony B. Candage , George Deliyannides
发明人： Anthony B. Candage , George Deliyannides
IPC分类号： H03K19/0185 , H03L5/00
CPC分类号： H03K19/018521
摘要： A translation circuit for mixed logic voltage signals is comprised of a first pair of self-biasing common-mode level shifters for receiving positive and negative polarity input signals respectively of a balanced input signal, each level shifter having a control input for receiving a ratio control signal, and having first level shifter nodes for providing the same polarity output signals, a second pair of self-biasing common-mode level shifters, each connected in parallel with a corresponding variable ratio level shifter, the second pair of level shifters having fixed level shift ratios, a circuit connected to level shifter nodes of the second pair of level shifters for providing and storing a signal which is a sum of voltages appearing at the level shifter nodes, and a circuit for applying the stored signal to the control inputs.
摘要翻译：用于混合逻辑电压信号的转换电路包括用于分别接收平衡输入信号的正极性和负极性输入信号的第一对自偏置共模电平移位器，每个电平移位器具有用于接收比率控制的控制输入信号，并具有用于提供相同极性输出信号的第一电平移位器节点，第二对自偏置共模电平移位器，每一个均与相应的可变比率电平移位器并联，第二对电平移位器具有固定电平连接到第二对电平移位器的电平移位器节点的电路，用于提供和存储作为出现在电平移位器节点处的电压之和的信号，以及用于将存储的信号施加到控制输入端的电路。

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