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    • 1. 发明授权
    • Automatic white balance system and automatic white balance control method
    • 自动白平衡系统和自动白平衡控制方式
    • US07864222B2
    • 2011-01-04
    • US11939179
    • 2007-11-13
    • Akira YoshinoKeiichiro YanagidaNoriko Matsuo
    • Akira YoshinoKeiichiro YanagidaNoriko Matsuo
    • H04N9/73
    • H04N9/735
    • An automatic white balance system according to an embodiment of the invention comprises a color separation and synchronization unit which has a line memory for generating a white-balance-adjusted YUV signal, a color judgment unit which judges whether or not a white balance adjustment is needed, a white balance adjustment gain computation unit which calculates a white balance adjustment gain on the basis of the result of the judgment at the color judgment unit and the white-balance-adjusted YUV signal, a reciprocal computation unit which outputs the reciprocal transformation value of the white balance adjustment gain, and a second multiplier which multiplies the white-balance-adjusted YUV signal by the reciprocal transformation value.
    • 根据本发明的实施例的自动白平衡系统包括:色分离同步单元,具有用于产生白平衡调节的YUV信号的行存储器;颜色判断单元,判断是否需要白平衡调整 白平衡调整增益计算单元,其基于颜色判断单元和白平衡调节的YUV信号的判断结果来计算白平衡调整增益;倒数计算单元,其输出 白平衡调整增益,以及将白平衡调整的YUV信号乘以相互变换值的第二乘法器。
    • 6. 发明申请
    • Method for controlling nonvolatile memory device
    • 用于控制非易失性存储器件的方法
    • US20070014155A1
    • 2007-01-18
    • US11486295
    • 2006-07-14
    • Akira Yoshino
    • Akira Yoshino
    • G11C16/04G11C11/34
    • G11C16/0483G11C16/0466G11C16/10H01L27/115
    • Data is written to a nonvolatile memory device having a memory region of four bits or larger in one memory cell sandwiched by a source and a drain with an improved accuracy. The nonvolatile memory device includes four control gates provided between a first and a second impurity-diffused regions that are provided separately from the semiconductor substrate, and a memory cell including memory regions that are counterpart of the control gates. A method for controlling the nonvolatile memory device includes classifying the four control gates into two groups of right and left sides, and then, applying a lower voltage to an impurity-diffused region that is further from a target memory region for injecting an electron and applying a higher voltage to an impurity-diffused region that is closer the target memory region, and applying a higher voltage, the higher voltage being higher than voltages applied to other control gates.
    • 在具有提高的精度的源极和漏极夹持的一个存储单元中,将数据写入具有四位或更大存储区的非易失性存储器件。 非易失性存储器件包括设置在与半导体衬底分离设置的第一和第二杂质扩散区域之间的四个控制栅极,以及包括与控制栅极对应的存储区域的存储单元。 用于控制非易失性存储器件的方法包括将四个控制栅极分成两组左右两侧,然后将较低的电压施加到远离用于注入电子的目标存储区域的杂质扩散区域并施加 对于更靠近目标存储区域的杂质扩散区域施加更高的电压,并且施加更高的电压,该较高的电压高于施加到其它控制栅极的电压。
    • 7. 发明授权
    • Nonvolatile semiconductor memory device, manufacturing method thereof, and operating method thereof
    • 非易失性半导体存储器件及其制造方法及其操作方法
    • US06888194B2
    • 2005-05-03
    • US10374840
    • 2003-02-26
    • Akira Yoshino
    • Akira Yoshino
    • H01L21/8247G11C16/04H01L21/28H01L21/8246H01L27/115H01L29/788H01L29/792
    • H01L27/11568G11C16/0475H01L21/28282H01L27/115H01L29/7923
    • Nonvolatile memory elements are disclosed which can have increased capacity, reduced operating voltage and/or faster operating speeds. According to one embodiment, a nonvolatile memory element can include a first diffusion layer (2) and a second diffusion layer (3) formed in a main surface of a substrate (1). A laminate film can be formed near a first diffusion layer (2) and/or a second diffusion layers (3) that includes a first insulating film (4a or 4), a second insulating film (5a or 5), and a third insulating film (6a or 6). A gate insulating film (7) can be formed a channel region and gate electrode (8) can be formed to cover gate insulating film (7) and the laminate film(s) that has a T-shape. A gate electrode (8) can have end portions that sandwich a first insulating film (4a or 4), a second insulating film (5a or 5), and a third insulating film (6a or 6) with a first diffusion layer (2) and/or second diffusion layer (3).
    • 公开了可以具有增加的容量,降低的操作电压和/或更快的操作速度的非易失性存储器元件。 根据一个实施例,非易失性存储元件可以包括形成在基板(1)的主表面中的第一扩散层(2)和第二扩散层(3)。 可以在第一扩散层(2)和/或第二扩散层(3)附近形成层压膜,所述第二扩散层包括第一绝缘膜(4a或4),第二绝缘膜(5a或5) 第三绝缘膜(6a或6)。 栅极绝缘膜(7)可以形成沟道区,并且可以形成栅电极(8)以覆盖栅极绝缘膜(7)和具有T形的层压膜。 栅极(8)可以具有将第一绝缘膜(4a或4),第二绝缘膜(5a或5)和第三绝缘膜(6a或6)夹在第一扩散层 (2)和/或第二扩散层(3)。