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1. 发明申请

US20120249180A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120249180A1
公开(公告)日：2012-10-04
申请号：US13429056
申请日：2012-03-23
申请人： Takamasa SUZUKI , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura
发明人： Takamasa SUZUKI , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.
摘要翻译：本文公开了一种可用于电平移位电路的装置。该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路，第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管电源线，使第五晶体管不导通以使第一反相器停用;以及控制电路，被配置为在第一反相器停用期间防止输出端子进入电浮动状态。

2. 发明授权

US08638121B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08638121B2
公开(公告)日：2014-01-28
申请号：US13429056
申请日：2012-03-23
申请人： Takamasa Suzuki , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura
发明人： Takamasa Suzuki , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.
摘要翻译：本文公开了一种可用于电平移位电路的装置。该装置包括分别提供彼此不同的第一，第二和第三电源电压的第一，第二和第三电源线，第一和第二输入端子和输出端子，耦合到第一电源线的输出电路，第一和第二输入端子和输出端子，第一反相器，包括耦合到第一输入端子的输入节点和耦合到第二输入端子的输出节点，在第二和第三功率之间串联耦合到第一反相器的第一晶体管所述第一晶体管被导通以使所述第一反相器无效;以及控制电路，被配置为在所述第一反相器的停用期间防止所述输出端子进入电浮动状态。

3. 发明申请

US20110176379A1 SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF 审中-公开
标题翻译：具有开放式线型存储器单元阵列的半导体存储器件及其控制方法
公开(公告)号：US20110176379A1
公开(公告)日：2011-07-21
申请号：US13008408
申请日：2011-01-18
申请人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
发明人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.
摘要翻译：半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位在第二位线的数据写入时的第二本地数据线。

4. 发明授权

US07750712B2 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US07750712B2
公开(公告)日：2010-07-06
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

5. 发明申请

US20090146716A1 Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
标题翻译：定时控制电路，定时生成系统，定时控制方法和半导体存储器件
公开(公告)号：US20090146716A1
公开(公告)日：2009-06-11
申请号：US12314207
申请日：2008-12-05
申请人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
发明人： Akira Ide , Yasuhiro Takai , Akira Kotabe , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama
IPC分类号： H03H11/26
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.
摘要翻译：定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟延迟元件定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。定时信号延迟的变化减小。

6. 发明授权

US08860476B2 Semiconductor device using multi-phase clock signal and information processing system including the same 有权
公开(公告)号：US08860476B2
公开(公告)日：2014-10-14
申请号：US14158253
申请日：2014-01-17
申请人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00 , H03L7/081 , H03K5/159 , H03K5/13 , H03K5/00
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.

7. 发明申请

US20130057326A1 SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME 有权
标题翻译：使用多相时钟信号的半导体器件和包括其的信息处理系统
公开(公告)号：US20130057326A1
公开(公告)日：2013-03-07
申请号：US13598289
申请日：2012-08-29
申请人： Yoshimitsu YANAGAWA , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu YANAGAWA , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00 , H03H11/26
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
摘要翻译：本文公开了一种包括延迟线的装置，其包括级联的n个延迟电路和将输入时钟信号延迟k个周期的延迟线，以及基于n的至少一部分生成具有不同相位的多相时钟信号的路由电路输出从n个延迟电路输出的时钟信号。 n和k都是大于1的整数，最大公约数为1。

8. 发明申请

US20140132317A1 SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME 有权
标题翻译：使用多相时钟信号的半导体器件和包括其的信息处理系统
公开(公告)号：US20140132317A1
公开(公告)日：2014-05-15
申请号：US14158253
申请日：2014-01-17
申请人： Yoshimitsu YANAGAWA , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu YANAGAWA , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00 , H03K5/159
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
摘要翻译：本文公开了一种包括延迟线的装置，其包括级联的n个延迟电路和将输入时钟信号延迟k个周期的延迟线，以及基于n的至少一部分生成具有不同相位的多相时钟信号的路由电路输出从n个延迟电路输出的时钟信号。 n和k都是大于1的整数，最大公约数为1。

9. 发明授权

US08643413B2 Semiconductor device using multi-phase clock signal and information processing system including the same 有权
标题翻译：半导体器件采用多相时钟信号和信息处理系统，包括相同的
公开(公告)号：US08643413B2
公开(公告)日：2014-02-04
申请号：US13598289
申请日：2012-08-29
申请人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
摘要翻译：本文公开了一种包括延迟线的装置，其包括级联的n个延迟电路和将输入时钟信号延迟k个周期的延迟线，以及基于n的至少一部分生成具有不同相位的多相时钟信号的路由电路输出从n个延迟电路输出的时钟信号。 n和k都是大于1的整数，最大公约数为1。

10. 发明授权

US09725753B2 Biomolecule information analysis device 有权
公开(公告)号：US09725753B2
公开(公告)日：2017-08-08
申请号：US14122206
申请日：2011-05-31
申请人： Kazuo Ono , Tatsuo Nakagawa , Yoshimitsu Yanagawa , Takayuki Kawahara , Akira Kotabe , Riichiro Takemura
发明人： Kazuo Ono , Tatsuo Nakagawa , Yoshimitsu Yanagawa , Takayuki Kawahara , Akira Kotabe , Riichiro Takemura
IPC分类号： C12Q1/68 , G01N33/487
CPC分类号： C12Q1/68 , C12Q1/6869 , G01N33/48721 , C12Q2565/631
摘要： Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG. 1).

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