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1. 发明授权

US5711365A Shell molding apparatus 失效
标题翻译：外壳成型设备
公开(公告)号：US5711365A
公开(公告)日：1998-01-27
申请号：US626605
申请日：1996-04-02
申请人： Akio Shimizu , Taiti Yoshikawa , Hiroshi Suzuki , Shigeyuki Kinoshita , Keiji Wada , Yasuo Kawai
发明人： Akio Shimizu , Taiti Yoshikawa , Hiroshi Suzuki , Shigeyuki Kinoshita , Keiji Wada , Yasuo Kawai
IPC分类号： B22C13/08 , B22C17/00 , B22C15/02
CPC分类号： B22C17/00 , B22C13/08 , Y10T29/4927 , Y10T29/49272
摘要： A shell molding apparatus includes a lower die and an upper die. The lower die includes a plurality of shell molding inserts, each having the shape of a halved cylinder, spiny insert receiving recesses which are formed in undercut portions formed by curved surfaces of adjacent shell molding inserts, and spiny inserts retractably provided in the spiny insert receiving recesses, each spiny insert having a curved surface of the same curvature as the curved surface of the shell molding insert and provided with many protrusions on the curved surface. The upper die has a plurality of continuously formed recesses corresponding to the plurality of shell molding inserts of the lower die. The shell molding apparatus further includes a spiny insert actuating mechanism for projecting/retracting spiny inserts by operating withdrawal pins connected to the spiny inserts, a stopper mechanism for positioning the withdrawal pins at a position where the withdrawal pins exhibit the same thermal expansion, and a thermal expansion absorbing mechanism for the withdrawal pins. The shell molding apparatus further includes a sand releasing mechanism for preventing shell sand from stagnating between spiny insert receiving recesses and the spiny inserts, resulting in smooth performance of the spiny inserts.
摘要翻译：壳体成型装置包括下模和上模。下模具包括多个壳体模制插入件，每个壳体模制插入件具有半圆柱形的形状，多个插入件容纳凹槽，其形成在由相邻的外壳模制插入件的弯曲表面形成的底切部分中，以及可旋转地设置在多刺插入件凹槽，每个多刺插入物具有与壳模制插件的弯曲表面相同曲率的曲面，并且在弯曲表面上设置有许多突起。上模具具有多个连续形成的与下模的多个外壳模制插件对应的凹槽。外壳成型装置还包括用于通过连接到多刺插入件的操作提取销来突出/缩回多刺插入件的多刺插入致动机构，用于将取出销定位在提升销呈现相同热膨胀的位置的止动机构，以及退火针的热膨胀吸收机构。外壳成型设备还包括一个防砂壳，用于防止壳砂停滞在多刺插入物容纳凹槽和多刺插入物之间，从而使多刺插入物的平滑性能得以实现。

2. 发明授权

US08901568B2 Silicon carbide insulating gate type semiconductor device and fabrication method thereof 有权
标题翻译：碳化硅绝缘栅型半导体器件及其制造方法
公开(公告)号：US08901568B2
公开(公告)日：2014-12-02
申请号：US13381605
申请日：2011-02-07
申请人： Takeyoshi Masuda , Keiji Wada , Misako Honaga
发明人： Takeyoshi Masuda , Keiji Wada , Misako Honaga
IPC分类号： H01L29/24 , H01L29/78 , H01L29/06 , H01L29/66 , H01L29/10 , H01L29/16 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/41741 , H01L29/42372 , H01L29/66068
摘要： A termination configuration of a silicon carbide insulating gate type semiconductor device includes a semiconductor layer of a first conductivity type having a first main face, a gate electrode, and a source interconnection, as well as a circumferential resurf region. The semiconductor layer includes a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to ½ the thickness of at least the semiconductor layer. A silicon carbide insulating gate type semiconductor device of high breakdown voltage and high performance can be provided.
摘要翻译：碳化硅绝缘栅型半导体器件的端接构造包括具有第一主面，栅电极和源极互连的第一导电类型的半导体层以及周向复原区域。半导体层包括第二导电类型的主体区域，第一导电类型的源极区域，第二导电类型的接触区域和第二导电类型的周边复原区域。除了身体区域之外的圆周清理区域的一部分的宽度大于或等于至少半导体层的厚度的1/2。可以提供具有高击穿电压和高性能的碳化硅绝缘栅型半导体器件。

3. 发明授权

US08785301B2 Method of cleaning silicon carbide semiconductor 有权
标题翻译：清洁碳化硅半导体的方法
公开(公告)号：US08785301B2
公开(公告)日：2014-07-22
申请号：US13390869
申请日：2011-02-25
申请人： Keiji Wada , Takeyoshi Masuda , Tomihito Miyazaki , Toru Hiyoshi , Satomi Itoh , Hiromu Shiomi
发明人： Keiji Wada , Takeyoshi Masuda , Tomihito Miyazaki , Toru Hiyoshi , Satomi Itoh , Hiromu Shiomi
IPC分类号： H01L21/322 , H01L21/31
CPC分类号： H01L21/02052 , H01L21/02057 , H01L21/67051 , H01L29/1608 , H01L29/66068 , H01L29/7802
摘要： A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor.
摘要翻译：清洗SiC半导体的方法包括以下步骤：在SiC半导体的表面形成氧化膜，除去氧化物膜。在形成氧化膜的步骤中，使用浓度大于或等于30ppm的臭氧水形成氧化膜。成形步骤优选包括加热SiC半导体的表面和臭氧水中的至少一个的步骤。因此，可以获得能够对SiC半导体具有清洁效果的SiC半导体的清洗方法。

4. 发明授权

US08564017B2 Silicon carbide semiconductor device and method for manufacturing same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US08564017B2
公开(公告)日：2013-10-22
申请号：US13485423
申请日：2012-05-31
申请人： Misako Honaga , Takeyoshi Masuda , Keiji Wada , Toru Hiyoshi
发明人： Misako Honaga , Takeyoshi Masuda , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/66 , H01L21/337 , H01L29/15
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/1095 , H01L29/66068
摘要： A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j−N2j>N1d and N2j
摘要翻译：漂移层具有电流流动的厚度方向，并具有用于第一导电类型的杂质浓度N1d。身体区域设置在漂移层的一部分上，具有由栅电极切换的通道，具有用于第一导电类型的杂质浓度N1b，并且具有大于杂质的第二导电类型的杂质浓度N2b 浓度N1b。 JFET区域与漂移层上的体区附近配置，对于第一导电类型具有杂质浓度N1j，并且对于第二导电类型的杂质浓度N2j小于杂质浓度N1j。 N1j-N2j> N1d和N2j

5. 发明授权

US08513676B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08513676B2
公开(公告)日：2013-08-20
申请号：US13512459
申请日：2010-12-17
申请人： Shin Harada , Toru Hiyoshi , Keiji Wada , Takeyoshi Masuda
发明人： Shin Harada , Toru Hiyoshi , Keiji Wada , Takeyoshi Masuda
IPC分类号： H01L29/38
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02529 , H01L21/02609 , H01L21/049 , H01L21/2007 , H01L29/045 , H01L29/1608 , H01L29/518 , H01L29/66068 , H01L29/94
摘要： A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −3° and not more than +5° relative to a (0-33-8) plane in a direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm−3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.
摘要翻译：一种半导体器件包括：由碳化硅制成的衬底，其具有相对于（0-33-8）面的偏离角不小于-3°且不大于+ 5°的主表面， 10方向; 由碳化硅制成的p型层，通过外延生长形成在衬底的主表面上; 以及形成为与p型层的表面接触的氧化物膜。在p型层和氧化膜之间的界面10nm以内的区域中，氮原子浓度的最大值为1×1021cm-3以上。

6. 发明授权

US08513673B2 MOSFET and method for manufacturing MOSFET 有权
标题翻译： MOSFET和MOSFET制造方法
公开(公告)号：US08513673B2
公开(公告)日：2013-08-20
申请号：US13120890
申请日：2010-03-23
申请人： Keiji Wada , Shin Harada , Takeyoshi Masuda , Misako Honaga
发明人： Keiji Wada , Shin Harada , Takeyoshi Masuda , Misako Honaga
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/78
摘要： A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V.
摘要翻译： MOSFET包括碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。当绝缘膜的厚度不小于30nm且不大于46nm时，其阈值电压不大于2.3V。当绝缘膜的厚度大于46nm且不大于100nm时，其阈值电压大于2.3V且不大于4.9V。

7. 发明申请

US20130009171A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130009171A1
公开(公告)日：2013-01-10
申请号：US13634860
申请日：2010-12-20
申请人： Shin Harada , Makoto Sasaki , Taro Nishiguchi , Kyoko Okita , Keiji Wada , Tomihito Miyazaki
发明人： Shin Harada , Makoto Sasaki , Taro Nishiguchi , Kyoko Okita , Keiji Wada , Tomihito Miyazaki
IPC分类号： H01L29/161 , H01L21/20
CPC分类号： H01L29/7802 , H01L21/02002 , H01L21/02008 , H01L21/2007 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/66333 , H01L29/7395
摘要： A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.
摘要翻译：半导体器件具有半导体层和衬底。半导体层构成电流路径的至少一部分，并且由碳化硅制成。衬底具有支撑半导体层的第一表面和与第一表面相对的第二表面。此外，基板由具有4H型单晶结构的碳化硅制成。另外，在光致发光测定中，基板具有波长为500nm左右的峰值强度与波长390nm左右的峰值强度的比例为0.1以下的物性。以这种方式，获得具有低导通电阻的半导体器件。

8. 发明申请

US20120313112A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120313112A1
公开(公告)日：2012-12-13
申请号：US13490208
申请日：2012-06-06
申请人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
IPC分类号： H01L29/161
CPC分类号： H01L29/7802 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/41741 , H01L29/4236 , H01L29/45 , H01L29/66068 , H01L29/7813
摘要： A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×1016 cm−3 or more. A plurality of p type regions of p conductivity type located apart from one another in a direction perpendicular to a thickness direction of the drift layer are arranged in a region in the drift layer lying between the p type body region and the silicon carbide substrate.
摘要翻译： MOSFET包括碳化硅衬底，由碳化硅制成的漂移层，并且包括相对于{0001}面具有50°以上且65°以下的偏离角的主表面，以及形成在并与漂移层的主表面接触。漂移层包括形成为包括与栅氧化膜接触的区域的p型体区。 p型体区的杂质浓度为5×10 16 cm -3以上。在垂直于漂移层的厚度方向的方向上彼此分离的p导电类型的多个p型区域布置在位于p型体区域和碳化硅衬底之间的漂移层中的区域中。

9. 发明申请

US20120280255A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120280255A1
公开(公告)日：2012-11-08
申请号：US13522216
申请日：2011-10-25
申请人： Takeyoshi Masuda , Keiji Wada , Toru Hiyoshi
发明人： Takeyoshi Masuda , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/16 , H01L21/336
CPC分类号： H01L29/66734 , H01L21/02233 , H01L21/02255 , H01L21/02378 , H01L21/02529 , H01L21/0465 , H01L21/049 , H01L29/0623 , H01L29/086 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/41741 , H01L29/4236 , H01L29/45 , H01L29/66068 , H01L29/6634 , H01L29/66348 , H01L29/66727 , H01L29/7802 , H01L29/7813
摘要： An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.
摘要翻译： MOSFET包括碳化硅衬底，有源层，栅氧化物膜和栅电极。有源层包括通过向栅电极施加电压而在与栅极氧化膜接触的区域处形成反型层的主体区域。身体区域包括布置在反型层形成区域的低浓度区域，并且在反转层中包含低浓度杂质和与反转层中的载流子移动方向上的低浓度区域相邻的高浓度区域形成反型层的区域，并且含有浓度高于低浓度区域的杂质。

10. 发明申请

US20120235165A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120235165A1
公开(公告)日：2012-09-20
申请号：US13512459
申请日：2010-12-17
申请人： Shin Harada , Toru ` Hiyoshi , Keiji Wada , Takeyoshi Masuda
发明人： Shin Harada , Toru ` Hiyoshi , Keiji Wada , Takeyoshi Masuda
IPC分类号： H01L29/38 , H01L21/20
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02529 , H01L21/02609 , H01L21/049 , H01L21/2007 , H01L29/045 , H01L29/1608 , H01L29/518 , H01L29/66068 , H01L29/94
摘要： A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −° and not more than +5° relative to a (0-33-8) plane in a direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm−3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.
摘要翻译：一种半导体器件包括：由碳化硅制成的衬底，其具有相对于（0-33-8）面在01-10°内具有不小于-0且不大于+ 5°的偏离角的主表面方向; 由碳化硅制成的p型层，通过外延生长形成在衬底的主表面上; 以及形成为与p型层的表面接触的氧化物膜。在p型层和氧化膜之间的界面10nm以内的区域中，氮原子浓度的最大值为1×1021cm-3以上。

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